Highly Robust Flexible Vertical-Channel Thin-Film Transistors Using Atomic-Layer-Deposited Oxide Channels and Zeocoat Spacers on Ultrathin Polyimide Substrates

Abstract

Mechanically flexible vertical-channel-structured thin-film transistors (VTFTs) with a channel length of 200 nm were fabricated on 1.2 μm thick colorless polyimide (CPI) substrates. All layers composing the gate stacks were prepared by atomic-layer deposition (ALD) with a good step coverage, and the process thermal budget was designed below 180 °C. Zeocoat was introduced as a spacer material to improve the device characteristics by properly determining the process conditions for clearly forming the vertical sidewalls. The transfer characteristics of the fabricated flexible ZnO and IGZO VTFTs showed the field-effect mobility of 3.31 and 6.57 cm2 V–1 s–1, the threshold voltages of 2.34 and 1.52 V, the subthreshold swings of 1.42 and 0.34 V/dec, and I ON/I OFF of 1.13 × 104 and 5.16 × 105, respectively, after the postannealing at 150 °C. The threshold voltage shifts (ΔV TH) under positive and negative bias stresses (PBS and NBS) were estimated to be +1.0, +1.8 V and −1.8, −3.8 V for 104 s for ZnO and IGZO VTFTs, respectively. The flexible IGZO VTFTs delaminated by means of a laser lift-off process did not show any marked degradation in device characteristics under mechanically strained conditions at various radii of curvature (R c). The ΔV TH values were also estimated to be +1.2 and −2.1 V under PBS and NBS at R c of 1 mm, respectively, demonstrating stable bending reliability. Appropriate choices of spacer materials, optimization of patterning process for spacer patterns, and ALD process of IGZO active channel can be proposed as key process parameters for guaranteeing excellent device performance of the oxide-channel VTFTs in this work.

Progressive p-channel vertical transistors fabricated using electrodeposited copper oxide designed with grain boundary tunability

“…Notably, even though this mobility is the first reported value for a vertical transistor using a p-type oxide channel, the technical level for electrical performance is outstanding and even comparable to n-type vertical transistors. 18,22,39 In addition, it should be noted that the SS and on/off current ratio are preferably better than those from previously reported planar p-type transistors (Table S1, ESI †) and vertical n-type transistors. 40,41 The channel coating process provides extraordinarily good electrodeposition, and existing methods, such as conventional sputtering and sol-gel processes, cannot produce artificially vertically aligned GBs in the oxide channel layers.…”

“…21 For instance, Yoon et al reported flexible vertical oxide transistors with a combination of atomic layer deposited (ALD) IGZO channels and Zeocoat spacer layers showing good positive bias stress (PBS) and negative bias stress (NBS) behaviors. 22 Consequently, the choice of adequate spacer materials and optimization of the process for definition of the vertical channel with regards to the dry etching of spacer layers has been seriously considered. Nevertheless, to the best of our knowledge, there are still no reports of vertical thin-film transistors fabricated from p-type oxide materials, regardless of the preparation method and performance level.…”

Recent progress and perspectives on atomic‐layer‐deposited semiconducting oxides for transistor applications

“…Recent advances can be divided into two approaches. One is to exploit the full potential of TFTs with ALD‐derived n ‐channel oxide channels to verify the feasibility of using them as non‐planar structures such as vertical TFT (VTFT) 72–75 in AR/VR displays or three‐dimensional NAND flash memory. The other combines LTPS‐compatible high‐performance TFTs with an ALD‐derived n ‐type semiconducting channel layer through novel structures including heterostructures, 22–25 bilayers, 26 and hybrid channels 27,28 …”

“…The feasibility of VTFTs with an ALD‐derived IGZO channel layer on an ultra‐thin polyimide substrate was examined by Kim et al 73 The fabricated VTFTs consisted of sputtered ITO electrodes, a spin‐coated Zeocoat spacer, an ALD‐derived IGZO channel, and an Al 2 O 3 gate insulator (Figure 8A). The combination achieved reasonable electrical performance, with a μ FE of 6.6 cm 2 /Vs, a V TH of 1.52 V, an SS of 0.34 V/dec, and an I ON/OFF of 5.2 × 10 5 by adopting a Zeocoat spacer to ensure a smooth and clear surface for the vertical side wall (Figure 8B).…”

“…(C) Variations of transfer characteristics for the IGZO VTFTs by bending condition at various values of R C . Reprinted with permission 73 . Copyright 2019, American Chemical Society.…”