Highly productive PCRAM technology platform and full chip operation: Based on 4F²(84nm pitch) cell scheme for 1 Gb and beyond

A Phase Change Memory Chip Based on TiSbTe Alloy in 40-nm Standard CMOS Technology

“…It was also noticed that the present TST device is faster than that of the GST based on 42-nm technology [16]. This may be considered that the Ti-centered atomic motifs play the role of pinning the local structures in both a-and cSbTe phases, in which they act as nucleation centers during the phase transition.…”

“…But the operation current of the present TST device is greater than that of the GST device mentioned in Ref. [16]. So it is essential to further optimize the Ti-Sb-Te composition and the device structure to decrease the operation current.…”

“…Compared with the one-bipolar-junction-transistor-andone-resistor (1B1R) [15] and one-diode-and-one-resistor (1D1R) [16,17] structured memory cell, the one-transistorand-one resistor (1T1R) [18][19][20] memory cell is the simplest and the best compatible in process, in which only additional 2-3 masks accomplishing the chip integration though the cell size of 1T1R structure is larger than that of the 1B1R and 1D1R structures. In our previous work, an 8-Mb PCRAM experimental chip has been fabricated in a 130-nm 4-metal level standard CMOS technology [18].…”

Memory Select Devices

“…Both single-crystal Si [21] and poly-Si diodes [22][23][24] have been developed as a select device for PCM arrays. To operate PCM with diode selectors, diodes need to provide ON-current density above 8 MA/cm 2 and OFF-current density below 100 A/cm 2 .…”

“…It is believed that Si diode can be scaled beyond 20 or 10 nm. Poly-Si diode select devices have been integrated in PCM crossbar arrays [22], 3D vertical chain-cell type PCM [23], and a 1 Gb PCM test chip [24]. A major challenge of Si diodes is the high processing temperature (above 1000°C) required to crystallize Si to reduce contact resistivity and OFF-current.…”