Highly parallel, fast scaling of numbers in nonredundant residue arithmetic

Ulman, Z.; Czyżak, Maciej

doi:10.1109/78.655432

Cited by 21 publications

(19 citation statements)

References 13 publications

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“…By decomposing the binary word of (24) into its weighted bit variables and applying Property 4 to each binary bit variable, we have (25) The last term of (25) can be simplified to (26) By substituting (23) and (25) into (21), (27) It is noted that is asserted in only one out of the combinations and when it is asserted, the remaining bits of are zeros. According to Property 4, the CEAC in each stage of CSA will introduce a constant bias of .…”

Section: Low and Chang: A Vlsi Efficient Programmable Power-ofmentioning

confidence: 99%

“…Efficient scaling algorithms in RNS have been developed and can be categorized into three main groups [20]: scaling by subset of the moduli set [17], [21], [23]- [26], scaling by a factor that is co-prime with the moduli set [20], [22], [27], and scaling by the power-of-two [17], [28], [29]. Although scaling by a fixed factor in RNS is not without difficulty when it comes to hardware implementation, the problem has been adequately solved for the three moduli set with a scaling factor [17].…”

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confidence: 99%

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A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Low

Chang

2012

IEEE Trans. Circuits Syst. I

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Variable scaling by power-of-two factor is the backbone operation of floating point arithmetic and is also commonly used in fixed-point digital signal processing (DSP) system for overflow prevention. While this operation can be readily performed in binary number system, it is extremely difficult to implement in residue number system (RNS). In the absence of an efficient solution to scale an integer directly in residue domain by a programmable power-of-two factor, improvised architecture by cascading fixed RNS scaling-by-two blocks has been previously presented. However, its area complexity and time complexity are worse than a hybrid solution leveraging on binary shifting through efficient residue-to-binary and binary-to-residue conversions. This paper presents a new algorithm for scaling in RNS by a programmable power-of-two factor. The proposed scaling algorithm breaks the inter-modulus dependency and produces a parallel architecture incurring no more than two logarithmic shifters, one-stage of carry-save adder and a modulo adder in any modulus channel. Comparing with the only available and most efficient hybrid programmable power-of-two scaler for the same moduli set, our proposed design has not only significantly reduced the critical path delay by 52.2%, 52.8%, 53.1%, and 53.2% for , 6, 7, and 8, respectively, but also cut down the area by 14.1% on average based on CMOS 0.18 standard cell based implementation. In addition, our proposed design has effectively reduced the total power consumption by 43.8% and the leakage power by 20.6% on average. Index Terms-Digital signal processing, power of two, residue number system, scaling.

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Section: Low and Chang: A Vlsi Efficient Programmable Power-ofmentioning

confidence: 99%

mentioning

confidence: 99%

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Low

Chang

2012

IEEE Trans. Circuits Syst. I

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“…General multiplications are also easier to perform because their standard realizations are small or segmentation of operands can be used for the combinatorial realization. It is worth mentioning that moduli with l < 7 may provide for the dynamic ranges over 90 bits [7]. The additional advantage of the RNS is the possibility of reducing power dissipation in CMOS circuits which is due to the lower switching activity and reduction of supply voltages [9].…”

Section: Introductionmentioning

confidence: 99%

Pipelined Two-Operand Modular Adders

Czyżak¹,

Horiszny²,

Smyk³

2015

RADIOENGINEERING

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“…The former method usually involves computationally intensive base extension operation [7], [9] although the outputs are free from scaling error. On the other hand, CRT-based approaches [5], [6], [8] usually produce scaled integer with some fractional error. All the aforementioned RNS scaling algorithms are 1 Intermodular operations refer to operations in RNS that require the information of all residue channels in order to produce the correct output results.…”

Section: Introductionmentioning

confidence: 99%

A new RNS scaler for {2n − 1, 2n, 2n + 1}

Low

Chang

2011

2011 IEEE International Symposium of Circuits and Systems (ISCAS)

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This paper presents an efficient RNS scaling algorithm for the balanced special moduli set { } 2 1, 2 , 2 1 n n n − + . By exploiting the relationship between the scaling constant and the residues of the three-moduli set using the New Chinese Remainder Theorem I (New CRT-I), the complicated modulo reduction operations for large integer scaling in RNS can be greatly simplified. The scaling constant has been chosen as ( ) 2 2 1 n n + such that all residues of the scaled integer areidentical and equal to the scaled integer output. This is particularly useful as no expensive and slow residue-to-binary converter is required for interfacing with conventional number system after the digital signal processing and scaling in RNS domain. The scaling error occurs only conditionally and is proven to be at most unity. The proposed design can be implemented entirely based on full adders with complexity commensurate with a multi-operand modulo 2 1 n − adder. Its area-time complexity is at least 86% lower than one of the fastest ROM-based scaler designs for the same moduli set over a wide dynamic range of 15 bits and above. I.978-1-4244-9474-3/11/$26.00 ©2011 IEEE

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Highly parallel, fast scaling of numbers in nonredundant residue arithmetic

Cited by 21 publications

References 13 publications

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Pipelined Two-Operand Modular Adders

A new RNS scaler for {2<sup>n</sup> − 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}

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Highly parallel, fast scaling of numbers in nonredundant residue arithmetic

Cited by 21 publications

References 13 publications

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

A VLSI Efficient Programmable Power-of-Two Scaler for $\{2^{n}-1,2^{n},2^{n}+1\}$ RNS

Pipelined Two-Operand Modular Adders

A new RNS scaler for &#x007B;2<sup>n</sup> &#x2212; 1, 2<sup>n</sup>, 2<sup>n</sup> + 1&#x007D;

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A new RNS scaler for {2<sup>n</sup> − 1, 2<sup>n</sup>, 2<sup>n</sup> + 1}