Highly linear wide‐swing continuous tuning of CMOS transconductors

Self Cite

A novel G m -C filter design technique is presented. It is based on floating-gate metal oxide semiconductor (FGMOS) transistors and consists in a topological rearrangement of conventional fully differential G m -C structures without modifying the employed transconductors at transistor level. The proposed method allows decreasing the number of active elements (transconductors) of the filter. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Drawbacks inherent to the use of FGMOS transistors are analyzed, such as large occupied area, high sensitivity to mismatch, or parasitic zeros in transfer functions. The features of the proposed technique are fully exploited in all-pole G m -C filter design, specially implementing unity gain Butterworth transfer functions. Thus, two low-power second-order Butterworth G m -C filters have been designed and fabricated to compare the proposed FGMOS technique with their equivalent topologies obtained by a conventional design method. Measurement results for a test chip prototype in a 0.5-μm standard complementary MOS process are presented, confirming the advantages of the proposed FGMOS design technique. open-loop operation and the use of simpler topologies. However, these benefits come with the difficulty of achieving high linearity [4].Besides, the growing density of integration in CMOS technologies is reducing the thickness of the gate oxide of transistors, so supply voltages are also decreasing for reliability reasons: Voltages of 0.9 V are employed in modern technologies such as 90 nm and 65 nm, and the tendency is to keep decreasing. Furthermore, the growing proliferation of wireless and portable devices is leading to an intensive research on low-power integrated circuits for extending the lifetime of batteries.Thus, two challenging tasks are associated to G m -C filter design: linearity improvement to satisfy the modern communication standards and adaptation to the current low-voltage low-power requirements. Aimed to these goals, a novel G m -C filter design technique based on floating-gate MOS (FGMOS) transistors is proposed in this paper. It consists in a topological rearrangement of conventional filters without modifying the transconductor implementation and allows improving the filter linearity and relaxing the trade-off between the power consumption and the input range of the operational transconductance amplifier (OTA).The paper is organized as follows. In Section 2, an overview of several G m -C filter design methods available in the technical literature is presented. In Section 3, the fundamentals of the proposed FGMOS technique are explained, and considerations for applying it to G m -C filter design are discussed. The second-order effects of the presented method are studied in Section 4. In Section 5, a conventional second-order Butterworth G m -C filter is compared with its equivalent implementation obtained using the proposed design technique. Finally, conclusions are drawn in Section 6. All the proposed circuits have been fabrica...

Section: Design Techniques At Basic Cell Level (Transconductor)mentioning

confidence: 99%

mentioning

confidence: 99%

Balanced G_m‐C filters with improved linearity and power efficiency

Algueta-Miguel

Blas

Lopez-Martin

2014

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“…The input signal is directly fed to the input of the first transconductor, and also the other transconductors are fed by full‐swing signals (Figure ). A straightforward way to improve linearity is to use source degeneration in the differential pair, by using either a resistance or MOS transistors operating in the triode region, as in . Topologies presented in are based on polynomial distortion cancelation by using two cross‐coupled differential pairs with different transconductance and distortion coefficients.…”

Section: Optimization Of Transconductors and Transistor‐level Designmentioning

confidence: 99%

High‐tuning‐range CMOS band‐pass IF filter based on a low‐Q cascaded biquad optimization technique

Monsurrò

Pennisi

Scotti

et al. 2014

Summary A design procedure for high‐order continuous‐time intermediate‐frequency band‐pass filters based on the cascade of low‐Q biquadratic cells is presented. The approach is well suited for integrated‐circuit fabrication, as it takes into account the maximum capacitance spread dictated by the available technology and maximum acceptable sensitivity to component variations. A trade‐off between noise and maximum linear range is also met. A novel, wide‐tuning‐range transconductor topology is also described. Based on these results, a 10‐pole band‐pass filter for a code division multiple‐access satellite receiver has been designed and tested. The filter provides tunable center frequency (f0) from 10 to 70 MHz and exhibits a 28‐MHz bandwidth around f0 = 70 MHz with more than 39‐dB attenuation at f0/2 and 2f0. Third‐order harmonic rejection is higher than 60 dB for a 1‐Vpp 70‐MHz input, and equivalent output noise is lower than 1 mVrms. The circuit is fabricated in a 0.25‐µm complementary metal oxide semiconductor process, and the core consumes 12 mA from a 2.5‐V supply, offering the best current/pole ratio figure. The die area resulted to be 0.9 × 1.1 mm2. Copyright © 2014 John Wiley & Sons, Ltd.

“…So far, many techniques have been presented to linearize an OTA. Adaptive biasing, resistive source/gate degeneration with the passive or active resistors, using cross‐coupled differential pairs, and various methods of derivative superposition are the main techniques that have been used to linearize OTAs . In some cases, two or more techniques are combined to obtain higher linearity .…”

Section: Introductionmentioning

confidence: 99%

Analysis and design of highly linear triode‐mode based OTA and its application to a wide tunable Gm‐C filter

Rezaei

Carvajal

2017

In this paper, a new highly linear operational transconductance amplifier (OTA) based on triode-mode input transistors is introduced. An analysis based on theoretical relations and simulation results is presented that aims to obtain the best operating points of triode-mode and cascode transistors to achieve the highest linearity. The proposed analysis is utilized to design a linear pseudo-differential OTA, benefiting a linear common mode feedforward and an appropriate common mode feedback circuit. The common mode feedforward circuit is also regulated in the same manner as main the transconductor to stabilize the output common mode voltage during tuning action and achieve higher common mode rejection ratio. Proposed OTA is used to implement a tunable low-power linear Gm-C filter. The cutoff frequency of the filter is tunable from 2.7 to 44 MHz while its power consumption changes from 3.5 to 8.5 mW in the entire tuning range. By applying input voltages up to 1.1 Vp-p, the filter's IM3 remains less than −48 dB for various cutoff frequencies. The proposed OTA and filter are simulated in 0.18-m CMOS technology with Hspice simulator.