Highly-linear FPGA-based Data Acquisition System for Multi-channel SiPM Readout

Townsend, Todd; Tang, Yuxuan; Chen, Jinghong

doi:10.22323/1.370.0094

Cited by 3 publications

(1 citation statement)

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“…Additionally, the input stage detects the input event and sends an enabling signal to the next blocks of the TDC to inform them about receiving a new input signal. Different mechanisms have been proposed for the input stage [ 36 , 37 , 38 ]. Most of them consider the input signal as the clock of the flip-flop (FF).…”

Section: Introductionmentioning

confidence: 99%

A Low-Resources TDC for Multi-Channel Direct ToF Readout Based on a 28-nm FPGA

Parsakordasiabi

Vornicu

Rodríguez-Vázquez

et al. 2021

Sensors

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In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources.

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Section: Introductionmentioning

confidence: 99%