An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA

Parsakordasiabi, Mojtaba; Vornicu, Ion; Rodríguez-Vázquez, Á.; Carmona-Galán, Ricardo

doi:10.1109/tim.2021.3136267

Cited by 11 publications

(6 citation statements)

References 56 publications

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“…Table 2 compares the work's technical specifications with those of similar TDC in recent years. In terms of the dead time, there are a minimum of two clock cycles in other schemes, except for one cycle in this work and the literature [29]. As for the resolution and accuracy, this study is slightly inferior to the literature [37,40], but the resource overhead of a single chain is lower than the literature [40].…”

Section: Experimental Comparison Of Tdc In Recent Yearsmentioning

confidence: 74%

“…Measurement accuracy (𝜎) is an essential parameter that reflects the existence of differences between the measured and expected values [36]. It is usually expressed by the stability of the measured value [29], i.e. quantified by the RMS error, as follows:…”

Section: Measurement Accuracymentioning

confidence: 99%

“…An interleaved scheme consisting of multiple TDCs was established to meet the required high throughput rate [28], whereas the resource overhead of the scheme increased several times from that of a single TDC. In 2022, M. Parsakordasiabi et al presented a dual-mode TDL approach to halve the dead time [29], but there is a higher probability of metastability. Furthermore, the error might affect the regular operation of the entire TDC system in severe cases.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, a modified pulse-holding circuit ensures that the dead time is reduced to one cycle, while lowering the probability of metastability in comparison to the literature [29]. A "hybrid" tapped sampling sequence based on the mainstream sampling sequence ("SCSC") is proposed to decrease the ultra-wide cells and optimize the nonlinear parameters.…”

Section: Introductionmentioning

confidence: 99%

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Design of a high-accuracy time-to-digital converter based on dual-edge signals

et al. 2023

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Among numerous time-to-digital converters (TDC), tapped delay line (TDL) is the most commonly used architecture. However, its dead time of more than two cycles is inefficient for applications with high measurement rates. Limited by the device process, the delay of each cell in the TDL exhibits a random and uneven distribution, degrading the linearity of the TDC. In this study, a dual-edge TDL structure is proposed. By improving original pulse-holding circuit, the propagated signal injected into the fine measurement chain is alternately switched between rising and falling edge signals to decrease the dead time to one cycle. The nonlinearity problem is alleviated by an enhanced tapped sampling sequence circuit. A dual-edge “1” count encoder is introduced to effectively simplify the difficulty of addressing the bubble problem. Bit-by-bit calibration and a moving average filter are adopted to improve accuracy. The proposed scheme has been verified on a Xilinx Kintex-7 FPGA platform. The resolution (least significant bit, LSB1) is 12.07 ps when the propagated signal in the TDL is the rising edge. The differential nonlinearity (DNL) is [-0.81,0.93] LSB1, and the integral nonlinearity (INL) is between [-2.33,2.19] LSB1. At the falling edge, the resolution (LSB0) is 11.90 ps, between [-0.73,0.98] LSB0 and [-2.46,1.83] LSB0 for DNL and INL, respectively. In addition, the accuracy reaches 15.25 ps after multiple measurements for different time intervals separately.

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Section: Experimental Comparison Of Tdc In Recent Yearsmentioning

confidence: 74%

Section: Measurement Accuracymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Design of a high-accuracy time-to-digital converter based on dual-edge signals

et al. 2023

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“…7. Many different calibration techniques have been reported to improve the linearity of the delay line based TDCs [24], [25], [26], [27]. However, these techniques require hundreds or even thousands of additional LUTs and DFFs.…”

Section: B Time-to-digital Converter and Pulse Width Encodermentioning

confidence: 99%

TROT: A Three-Edge Ring Oscillator Based True Random Number Generator With Time-to-Digital Conversion

Grujić

Verbauwhede

2022

IEEE Trans. Circuits Syst. I

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This paper introduces a new true random number generator (TRNG) based on a three-edge ring oscillator. Our design uses a new technique with a time-to-digital converter to effectively acquire jitter accumulated independently by each edge. As a part of the security evaluation, we present the stochastic model of the TRNG's digital noise source and estimate a lower bound of the min-entropy per random bit. Starting from the obtained entropy bound, we propose a procedure for selecting and implementing an area-efficient and throughput-optimal postprocessing function based on the best known linear codes that will increase the output min-entropy rate to more than 0.999. The proposed TRNG exquisitely balances low design effort and resource consumption with high throughput and a high minentropy rate, making it more suitable for randomness-demanding and resource-constrained platforms than the state-of-the-art.The complete implementation of the TRNG digital noise source and the post-processing occupies 33 slices and achieves a throughput of 12.5 Mbps on Xilinx Zynq-7000 FPGAs. The min-entropy of the generated random bits is assessed by NIST SP 800-90B entropy estimators, and the tested sequences pass the AIS-31 and the NIST SP 800-22 test suits.

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An FPGA-based 48-channel, 250 mega samples per second throughput time measurement system

Zhou

Yan

et al. 2023

Nuclear Instruments and Methods in Physics Research Section A:

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An Efficient TDC Using a Dual-Mode Resource-Saving Method Evaluated in a 28-nm FPGA

Cited by 11 publications

References 56 publications

Design of a high-accuracy time-to-digital converter based on dual-edge signals

Design of a high-accuracy time-to-digital converter based on dual-edge signals

TROT: A Three-Edge Ring Oscillator Based True Random Number Generator With Time-to-Digital Conversion

An FPGA-based 48-channel, 250 mega samples per second throughput time measurement system

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