Highly area efficient and cost effective double stacked S/sup 3/(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM

Jung, Soon‐Moon; Lim, Hyun Suk; Cho, Wonseok; Cho, Hoosung; Yeo, Chadong; Kang, Y.M.; Bae, Dong-il; Na, Jonghoon; Kwak, Kyung Won; Choi, Bok Kyoung; Kim, Sung Jin; Jeong, Jae−Hun; Chang, Young‐Jin; Jang, Jaehoon; Kim, Jonghyuk; Kim, Kinam; Ryu, Byung-Il

doi:10.1109/iedm.2004.1419128

Cited by 6 publications

(1 citation statement)

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“…A 3D-stacked SRAM has been fabricated by the lateral solid phase epitaxial growth as shown in Fig. 22 [51]. 3D NAND Flash memories have been fabricated using poly-Si thin film transistors (TFTs) as memory transistors.…”

Section: D-stacked Cmos Image Sensormentioning

confidence: 99%

Recent progress in 3D integration technology

Koyanagi

2015

IEICE Electron. Express

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3D integration technology is the key for future LSIs with highperformance, low-power and multi-functionality. Especially, to mitigate various concerns caused by device scaling down to 10 nm or less, it is indispensable to introduce a new concept of heterogeneous 3D integration in which various kinds of materials, devices and technologies are integrated on a Si substrate. Future prospects of such a heterogeneous 3D integration technology has been discussed representing typical examples of heterogeneous 3D LSIs after the present situation of 3D integration technology is described.

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Section: D-stacked Cmos Image Sensormentioning

confidence: 99%