2022
DOI: 10.1038/s41586-022-04588-2
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High-κ perovskite membranes as insulators for two-dimensional transistors

Abstract: High-κ perovskite membranes as insulators for two-dimensional transistors. Nature, 605(7909), 262-267.

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Cited by 170 publications
(144 citation statements)
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“…14 shows the typical dual-sweep transfer curves of our devices. The normalized hysteresis width is 40 mV/MV cm −1 , which is on par with reported hysteresis values and indicates the presence of low border traps and interface states 39 .
Fig.
…”
Section: Resultssupporting
confidence: 79%
“…14 shows the typical dual-sweep transfer curves of our devices. The normalized hysteresis width is 40 mV/MV cm −1 , which is on par with reported hysteresis values and indicates the presence of low border traps and interface states 39 .
Fig.
…”
Section: Resultssupporting
confidence: 79%
“…[ 1 ] Consequently, dramatic attention has been drawn to employing new semiconductor materials or novel device architectures as alternative routes to replace conventional silicon‐based electronics, aiming to realize the continued growth and miniaturization of information technology. [ 2–4 ]…”
Section: Introductionmentioning
confidence: 99%
“…The integration of these freestanding complex oxides with 2D materials, however, was not reported until very recently by two research groups in parallel with preparation of our work. In these two recent works , SrTiO 3 (STO) thin layers are isolated freestanding and used as high-κ dielectrics for field-effect transistors based on 2D materials. Yang et al show that in devices utilizing a freestanding layer of STO, ON/OFF ratios of 10 8 and subthreshold swings of 66 mV/dec can be achieved .…”
mentioning
confidence: 99%
“…Huang et al. show that the STO layer is exceptional for use as a dielectric layer because it possesses a subone-nanometer capacitance equivalent thickness with a low leakage current (less than 10 –2 A·cm –2 at 2.5 MV·cm –1 ) …”
mentioning
confidence: 99%
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