High-yield performance-efficient redundancy analysis for 2D memory

Abstract

High-yield performance-efficient remapping architecture, repairing algorithms and redundancy analysis (HYPERA) are proposed for 2D memory. The proposed hypercube-based memory repair architecture consists of spare row-like subcubes with a modified ternary CAM with an address concentrator and a parallel sorter-like address concentrator. Generally, for an acceptable repair rate about 3% of spare subcubes and no more than 5% of hardware overhead are required. A modified Quine-McCluskey algorithm and the Essential Cube Pivoting algorithm are also developed for redundancy analysis. Almost 100% of repair rate can be obtained using only 32 equivalent rows under reasonable situations. Under less spare memory the repair rates of proposed approaches can be much higher than most results of previous work. CitationHuang T C. High-yield performance-efficient redundancy analysis for 2D memory.

Novel modified memory built in self‐repair (MMBISR) for SRAM using hybrid redundancy‐analysis technique

“…The main objective of this work is to adopt the advantages of previously proposed MBISR [15, 16, 19, 20] and mitigating the limitations, while keeping a hawk eye on trade‐offs. The advantages and some checks are as described below:…”

“…In these designs, the MBISR hardware consists of three main modules i.e. memory built in self‐test module (MBIST) [19], memory SRAM device under test (DUT) module and built in self‐repair (BISR) module [20]. Apart from the BISR module, the functional behaviours of above two modules are same.…”