High-Yield Fabrication Process for 3D-Stacked Ultrathin Chip Packages Using Photo-Definable Polyimide and Symmetry in Packages

Abstract

Abstract-Getting output of multiple chips within the volume of a single chip is the driving force behind development of this novel 3D integration technology, which has a broad range of industrial and medical electronic applications. This goal is achieved in a two-step approach: at first thinned dies are embedded in a polyimide interposer with a fine-pitch metal fan-out resulting Ultra-Thin Chip Packages (UTCP), next these UTCPs are stacked by lamination.Step height at the chip edge of these UTCPs is the major reason of die cracking during the lamination. This paper contains an approach to solve this issue by introduction of an additional layer of interposer which makes it flat at the chip edge resulting in Flat-UTCP. In addition to that, randomness in non-functional package positions per panels reduces the overall yield of the whole process up to certain extend. A detailed analysis on these two issues to improve the process yield is given in this paper. 3D-stacked memory module composed of 4 EEPROM dies was processed and tested to demonstrate this new concept of enhanced fabrication yield.

Micro-Satellite Systems Design, Integration, and Flight

“…For the Alpha project, the picosatellite payload was developed by Dr. Van Hunter Adams [14,15], (previously at Cornell). The satellite is printed on a thin Kapton substrate [16,17] and only has a solar panel, processor, IMU, GPS, light sensor, and RF transceiver. The satellite is named ChipSat.…”

Material effect on thermal stress of annular-trench-isolated through silicon via (TSV)

“…The three-dimensional integrated circuit (3D IC) is becoming an attractive technology to accommodate multiple heterogeneous dies such as logic, memory, analog, RF, and micro-electrical mechanical systems (MEMS). [1][2][3] Through silicon via (TSV) provides a structure of vertical connection to shorten the transmission wire to reduce the RC delay, and thus the performance of the IC can be improved by lowering power consumption with a shortened wiring network. 4) 3D IC with TSV is expected to have a broad impact in areas such as networking, graphics, mobile communications, and computing, especially for applications that require ultra-light, small, lowpower devices.…”