High Voltage Devices and Circuits in Standard CMOS Technologies

Ballan, Hussein; Declercq, M.

doi:10.1007/978-1-4757-5404-9

Cited by 90 publications

(36 citation statements)

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“…The new levelshifter cell proposed comprises two coupled voltage mirrors, M_F2 and M_F1 [17], [21]- [23]. The former consists of an HV PMOS (M_F2), together with an LV NMOS (M_F14) connected in a diode configuration as the load.…”

Section: Description Of the New Level-shifter Cellmentioning

confidence: 99%

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Integrated Circuit Implementation for a GaN HFET Driver Circuit

Wang

Riva

Bakos

et al. 2010

IEEE Trans. on Ind. Applicat.

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Abstract-This paper presents the design and implementation of a new integrated circuit (IC) that is suitable for driving the new generation of high-frequency GaN HFETs. The circuit, based upon a resonant switching transition technique, is first briefly described and then discussed in detail, focusing on the design process practical considerations. A new level-shifter topology, used to generate the zero and negative gate-source voltages required to switch the GaN HFET, is introduced and analyzed. The experimental measurements included in this paper report the results of tests carried out on an IC designed and fabricated as part of the multiproject die in high-voltage process H35B4 of Austriamicrosystems. They fully demonstrate the performance of the proposed driver that opens the possibility of fully exploiting the wide capabilities and advantages of GaN devices for use in power electronics applications.Index Terms-GaN HFET, gate driver integrated circuit (IC), high frequency.

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Section: Description Of the New Level-shifter Cellmentioning

confidence: 99%

“…Fig. 5 shows the two-stage driver circuit implementing the low-standby-current positive-to-negative levelshifter cell [21]. An HV buffer stage is added between the HV NMOS transistor of the output stage and the static level shifter in order to reduce the standby static currents in the circuit.…”

Section: Description Of the New Level-shifter Cellmentioning

confidence: 99%

Integrated Circuit Implementation for a GaN HFET Driver Circuit

Wang

Riva

Bakos

et al. 2010

IEEE Trans. on Ind. Applicat.

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“…These HV transistors enable direct reuse of most older circuit architectures, running at supply voltages corresponding to the original design: high supply voltages when related to the nominal supply voltage of the CMOS process used. Extended-drain transistors that can be realized in standard CMOS could also be used; such structures are described in [28].…”

Section: A Solution: Living Outside Railsmentioning

confidence: 99%

Analog circuits in ultra-deep-submicron CMOS

Annema

Nauta

Langevelde

et al. 2005

IEEE J. Solid-State Circuits

353

149

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“…High-voltage (HV) CMOS process has been widely used in driver circuits, telecommunication, power switch, motor control systems, etc [1]. One tough challenge on reliability issue in HV CMOS process is to eliminate the possible occurrence of latchup [1]- [6].…”

Section: Introductionmentioning

confidence: 99%

“…One tough challenge on reliability issue in HV CMOS process is to eliminate the possible occurrence of latchup [1]- [6]. However, due to an ultra-high operating voltage, it's rather difficult to achieve the latchup-free purpose in HV CMOS ICs by raising the latchup holding voltage to exceed the normal circuit operating voltage.…”

Section: Introductionmentioning

confidence: 99%

Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

Hsu

Ker

Lin

et al. 2006

2006 IEEE International Reliability Physics Symposium Proceedings

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The dependence of device structures and layout parameters on latchup immunity in high-voltage (HV) 40-V CMOS process have been verified with silicon test chips and investigated with device simulation. It was demonstrated that a specific test structure considering the parasitic silicon controlled rectifier (SCR) resulting from isolated asymmetric HV NMOS and HV PMOS has the best latchup immunity. The test structures and simulation methodology proposed in this work can be applied to extract safe and compact design rule for latchup prevention in HV CMOS process. All the test chips are fabricated in a 0.25-μm 40-V CMOS technology.

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High Voltage Devices and Circuits in Standard CMOS Technologies

Cited by 90 publications

References 0 publications

Integrated Circuit Implementation for a GaN HFET Driver Circuit

Integrated Circuit Implementation for a GaN HFET Driver Circuit

Analog circuits in ultra-deep-submicron CMOS

Experimental Evaluation and Device Simulation of Device Structure Influences on Latchup Immunity in High-Voltage 40-V CMOS Process

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