High-Voltage Analog System for a Mobile NAND Flash

Kang, Yong‐Kook; Kim, Jin-Kook; Hwang, Sang Won; Kwak, Joon Young; Park, Jun-Young; Kim, Dae-Yong; Kim, Chan Ho; Park, Jong Yeol; Jeong, Yong-Taek; Baek, Jong Nam; Jeon, Su Chang; Jang, Pyungmoon; Lee, Sang Hoon; Lee, You-Sang; Kim, Minseok; Lee, Jin-Yub; Choi, Yun Ho

doi:10.1109/jssc.2007.914327

Cited by 32 publications

(14 citation statements)

References 13 publications

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“…Since the switching regulator switches the driving clock of the charge pump, the output ripple voltage is hard to avoid, and has the effect of widening the programmed cell distribution [4].…”

Section: High Voltage Generatormentioning

confidence: 99%

“…This will reduce the boosted channel program inhibit voltage, increasing the program stress and lowering endurance [4].…”

Section: High Voltage Generatormentioning

confidence: 99%

“…In order to have good PSR at high frequency, the DC gain and the bandwidth of the error amplifier (EA) of an H/V linear regulator have to be large, which is very challenging [4].…”

Section: High Voltage Generatormentioning

confidence: 99%

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H/V linear regulator with enhanced power supply rejection

Kim

Lee

2014

IEICE Electron. Express

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This letter describes a H/V linear regulator for enhancing power supply rejection (PSR) for generating the program/erase voltage. In order to reduce the ripple voltage of the H/V linear regulator, using an additional feedback technique is proposed. The proposed H/V linear regulator has dual loop feedback that improves loop gain and PSR. In the simulated PSR performance, À43.1 dB is observed with the proposed H/V linear regulator at 2.12 MHz. This result is 13 dB better than results obtained with the conventional H/V Linear regulator.

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Section: High Voltage Generatormentioning

confidence: 99%

“…This will reduce the boosted channel program inhibit voltage, increasing the program stress and lowering endurance [4].…”

Section: High Voltage Generatormentioning

confidence: 99%

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H/V linear regulator with enhanced power supply rejection

Kim

Lee

2014

IEICE Electron. Express

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“…Moreover, many voltages have a value larger than the NAND power supply, requiring the use of several charge pumps. In order to achieve a highly accurate estimation of the power consumption of each ISPP algorithm considered in this work we have simulated the following blocks of the NAND HV subsystem: Program Charge pump, Inhibit Charge pump, Verify Charge pump, Regulators and limiting systems, following the design in [15].…”

Section: Runtime-selection Of Program Algorithmmentioning

confidence: 99%

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

Zambelli¹,

Indaco²,

Fabiano³

et al. 2012

2012 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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In spite of the mature cell structure, the memory controller architecture of Multi-level cell (MLC) NAND Flash memories is evolving fast in an attempt to improve the uncorrected/miscorrected bit error rate (UBER) and to provide a more flexible usage model where the performance-reliability trade-off point can be adjusted at runtime. However, optimization techniques in the memory controller architecture cannot avoid a strict trade-off between UBER and read throughput. In this paper, we show that co-optimizing ECC architecture configuration in the memory controller with program algorithm selection at the technology layer, a more flexible memory sub-system arises, which is capable of unprecedented trade-offs points between performance and reliability.

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“…1. What's more, the intent of capacitor C f is to compensate the RC delay caused by R f2 and C fs [9]. Architecture of VD which will be discussed in the following part is also updated.…”

Section: Introductionmentioning

confidence: 99%

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology

Huang

Wang

Chen

et al. 2017

IEICE Electron. Express

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This paper represents a 4.5 V regulated charge pump with extremely small ripple. The pump designed with Voltage Doubler (VD) significantly reduces the output ripple voltage. In addition, this circuit utilizes a controllable pumping current (CPC) technology, which achieves automatically adjusting output current by feedback mechanism and resizing transfer transistors. The proposed charge pump has been demonstrated in 0.32 µm 3D NAND periphery technology under 3 V power supply. Simulation results show that the output ripple voltage is 1.2 mV at 5 mA load current with 0.1 µF load capacitance. The maximum current drivability and power efficiency is 8 mA and 81% respectively.

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High-Voltage Analog System for a Mobile NAND Flash

Cited by 32 publications

References 13 publications

H/V linear regulator with enhanced power supply rejection

H/V linear regulator with enhanced power supply rejection

A cross-layer approach for new reliability-performance trade-offs in MLC NAND flash memories

A 1.2 mV ripple, 4.5 V charge pump using controllable pumping current technology

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