High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems

Abstract

We describe an efficient, fully-parallel Network of Programmable Logic Array (NPLA)-based realization of iterative decoders for structured LDPC codes. The LDPC codes are developed in tandem with the underlying VLSI implementation technique, without compromising chip design constraints. Two classes of codes are considered: one, based on combinatorial objects derived from difference sets and generalizations of non-averaging sequences, and another, based on progressive edge-growth techniques. The proposed implementation reduces routing congestion, a major issue not addressed in prior work. The operating power, delay and chip-size of the circuits are estimated, indicating that the proposed method significantly outperforms presently used standard-cell based architectures. The described LDPC designs can be modified to accommodate widely different requirements, such as those arising in recording systems, as well as wireless and optical data transmission devices.

Design issues in the implementation of versatile, high‐speed iterative decoders

“…Some constraints are inserted to obtain an upper bound on the 'height' of the code, a parameter related to the interconnection resources needed for the routing of messages; the limitation of this metric leads to a reduction of the physical length of wires required on the decoder. The authors of Reference [25] address the issues of wiring overhead and routing congestion by designing the paritycheck matrix of the code in order to reduce the exchange of information between processors far apart in the decoder layout. A similar criterion has been chosen in Reference [26]: the parity-check matrix is composed of small identical modules placed along the diagonal in order to reduce the routing complexity of the decoder.…”

Generalized low-density parity-check codes for optical communication systems

“…Since the local components in this case can have large length and therefore large minimum distance as well, the minimum distance of the resulting GLDPC codes is very high. The third approach is an attractive idea in terms of possible practical partly-parallel very large scale integration (VLSI) implementations [21], since the same code structure can be reused on different levels.…”