VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

Fanucci, Luca; Ciao, P.; Colavolpe, Giulio

doi:10.1093/ietfec/e89-a.7.1976

Cited by 6 publications

(5 citation statements)

References 25 publications

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“…Note that a number of fully-parallel turbo decoders have been previously proposed, although these suffer from significant disadvantages that are not manifested in the proposed algorithm. In [14], the min-sum algorithm is employed to perform turbo decoding. However, this approach only works for a very limited set of turbo code designs, which does not include those employed by any standards.…”

Section: Introductionmentioning

confidence: 99%

A Fully-Parallel Turbo Decoding Algorithm

Maunder

2015

IEEE Trans. Commun.

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Abstract-This paper proposes a novel alternative to the Logarithmic Bahl-Cocke-Jelinek-Raviv (Log-BCJR) algorithm for turbo decoding, yielding significantly improved processing throughput and latency. While the Log-BCJR processes turboencoded bits in a serial forwards-backwards manner, the proposed algorithm operates in a fully-parallel manner, processing all bits in both components of the turbo code at the same time. The proposed algorithm is compatible with all turbo codes, including those of the LTE and WiMAX standards. These standardized codes employ odd-even interleavers, facilitating a novel technique for reducing the complexity of the proposed algorithm by 50%. More specifically, odd-even interleavers allow the proposed algorithm to alternate between processing the oddindexed bits of the first component code at the same time as the even-indexed bits of the second component, and vice-versa. Furthermore, the proposed fully-parallel algorithm is shown to converge to the same error correction performance as the stateof-the-art turbo decoding algorithm. Owing to its significantly increased parallelism, the proposed algorithm facilitates throughputs and latencies that are up to 6.86 times superior to those of the state-of-the art algorithm, when employed for the LTE and WiMAX turbo codes. However, this is achieved at the cost of a moderately increased computational complexity and resource requirement.

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Section: Introductionmentioning

confidence: 99%

A Fully-Parallel Turbo Decoding Algorithm

Maunder

2015

IEEE Trans. Commun.

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“…Equations ( 3) and ( 4) employ the Jacobian logarithm, which is defined for two operands as [8] max * ( δ1 , δ2 ) = max( δ1 , δ2 ) + ln 1 + e −|( δ1 − δ2 )| , (7) and may be extended to more operands by exploiting its associative property. Alternatively, the exact max * of ( 7) may be approximated by [27] max…”

Section: Nmentioning

confidence: 99%

Fully Parallel Turbo Equalization for Wireless Communications

2015

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“…In [20], a 1024-bit, fully parallel decoder is presented, achieving 1 Gbps throughput with logic density of only 50% to accommodate the complexity of interconnection: it comprises of 9750 wires with 3-bit quantization. None of the parallel implementations in [20][21][22] grant multimode flexibility due to wired connections. In addition, almost all existing fully parallel LDPC decoders are built on custom silicon, which precludes any prospect of reprogramming.…”

Section: Flexible Decodersmentioning

confidence: 99%

Flexible LDPC Decoder Architectures

Awais

Condo

2012

VLSI Design

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Flexible channel decoding is getting significance with the increase in number of wireless standards and modes within a standard. A flexible channel decoder is a solution providing interstandard and intrastandard support without change in hardware. However, the design of efficient implementation of flexible low-density parity-check (LDPC) code decoders satisfying area, speed, and power constraints is a challenging task and still requires considerable research effort. This paper provides an overview of state-of-the-art in the design of flexible LDPC decoders. The published solutions are evaluated at two levels of architectural design: the processing element (PE) and the interconnection structure. A qualitative and quantitative analysis of different design choices is carried out, and comparison is provided in terms of achieved flexibility, throughput, decoding efficiency, and area (power) consumption.

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VLSI Design of a Fully-Parallel High-Throughput Decoder for Turbo Gallager Codes

Cited by 6 publications

References 25 publications

A Fully-Parallel Turbo Decoding Algorithm

A Fully-Parallel Turbo Decoding Algorithm

Fully Parallel Turbo Equalization for Wireless Communications

Flexible LDPC Decoder Architectures

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