High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme

Polar codes have recently emerged as an error-correcting code and have become popular owing to their capacity-achieving nature. Polar code based communication system primarily consists of two parts, including Polar Encoder and Decoder. Successive Cancellation Decoder is one of the methods used in the decoding process. The Successive Cancellation Decoder is a recursive structure built with the building block called Processing Element. This article proposes a low power, area-efficient architecture for the Successive Cancellation Decoder for polar codes. Successive Cancellation Decoder with code length 1024 and code rate 0.5 was designed in Verilog HDL and implemented using 45-nm CMOS technology. The proposed work focuses on developing an area-efficient Successive Cancellation Decoder architecture by presenting a new Processing Element architecture. The proposed architecture has produced about 35% lesser area with a 12% reduced gate count. Moreover, power is also reduced by 50%. A substantial reduction in the latency and improvement in the Technology Scaled Normalized Throughput value was observed.

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“…represents the encoded value [12]. The position of frozen bits are identified by the method explained in [4].…”

Section: Polar Code -Encodingmentioning

confidence: 99%

Low Power, Area Efficient Architecture for Successive Cancellation Decoder

James

Lakshminarayanan

2022

EMITTER Int'l J. of Engin. Technol.

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“…The unrolled architecture proposed by Giard et al has produced a high-throughput in the decoder [5]. A novel merged processing element for SCD based on one's complement was proposed in [6] which helped to increase the throughput. In [7], a Novel simplified merged processing element (SMPE) architecture was proposed for SCD, and the decoding tree was constructed with low complexity.…”

Section: Introductionmentioning

confidence: 99%

“…Hardware performance of decoder with code length, N=1024DesignYuan and Parhi[4] Leroux et al[25] Kim et al[6] …”

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confidence: 99%

Successive cancellation decoding of polar codes using new hybrid processing element

James

Lakshminarayanan²

2022

IJRES

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Polar codes are one of the best linear block codes that are capacity achieving and incorporating along with it a simplified encoding and decoding routines. Successive cancellation (SC) algorithm is one of the predominantly used decoding algorithms due to its low complexity. It has broad scopes for hardware architecture design and reformulation. For polar code, the trade-off among the long latency and the silicon area of the SC algorithm is a bottleneck for the design of a high throughput polar decoder. The available prior SC polar decoder designs have higher area requirements for higher block length. This paper introduces a unique reformulation of the processing element (PE) block of SC decoding. The proposed reformulation leads to two benefits: firstly, critical path and hardware complexity of the PE are meaningfully reduced by using a unified adder block. Secondly, the silicon area requirement and the power consumption were also reduced considerably without any loss in performance. The proposed PE is used to build the decoder for various block lengths. Moreover, a Gate-level analysis of the proposed decoder has revealed that the design attains an 18% area reduction and 38% reduction in power consumption over the conventional one with similar performance.

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“…To date, much of this work has addressed the theoretical aspects of polar codes and is aimed at improving the error correction performance of polar decoders [2]. Several researchers have viewed the successive-cancellation (SC) algorithm as a good candidate for hardware design of polar decoders because of its low complexity [3][4][5][6]. The semi-parallel SC decoder of Leroux et al [4] has low-processing complexity, long latency and low throughput.…”

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confidence: 99%

Simplified merged processing element for successive‐cancellation polar decoder

Yun

Lee

2016

Electron. lett.

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Novel simplified merged processing element (SMPE) architectures to design a low-complexity successive-cancellation (SC) polar decoder are presented. The proposed SMPE architectures reduce the number of sign-magnitude conversions and switch networks, relative to those of the conventional merged processing element. Synthesis results show that the (1024, 512) SC polar decoder using the proposed SMPE architectures significantly decreases hardware complexity and improves technology scaled normalised throughput, as compared to those of the previously reported architectures.

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High-Throughput Low-Complexity Successive-Cancellation Polar Decoder Architecture using One's Complement Scheme

Cited by 10 publications

References 14 publications

Low Power, Area Efficient Architecture for Successive Cancellation Decoder

Low Power, Area Efficient Architecture for Successive Cancellation Decoder

Successive cancellation decoding of polar codes using new hybrid processing element

Simplified merged processing element for successive‐cancellation polar decoder

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