High-Throughput LDPC-Decoder Architecture Using Efficient Comparison Techniques & Dynamic Multi-Frame Processing Schedule

Abstract

This paper presents architecture of block-level-parallel layered decoder for irregular LDPC code. It can be reconfigured to support various block lengths and code rates of IEEE 802.11n (WiFi) wireless-communication standard. We have proposed efficient comparison techniques for both column and row layered schedule and rejection-based high-speed circuits to compute the two minimum values from multiple inputs required for row layered processing of hardware-friendly min-sum decoding algorithm. The results show good speed with lower area as compared to state-of-the-art circuits. Additionally, this work proposes dynamic multi-frame processing schedule which efficiently utilizes the layered-LDPC decoding with minimum pipeline stages. The suggested LDPC-decoder architecture has been synthesized and post-layout simulated in 90 nm-CMOS process. This decoder occupies 5.19 area and supports multiple code rates like 1/2, 2/3, 3/4 & 5/6 as well as block-lengths of 648, 1296 & 1944. At a clock frequency of 336 MHz, the proposed LDPC-decoder has achieved better throughput of 5.13 Gbps and energy efficiency of 0.01 nJ/bits/iterations, as compared to the similar state-of-the-art works. Index Terms-Data-rate/throughput, IEEE 802.11n (WiFi) wireless-communication standard and very-large scale-integration (VLSI) design, LDPC codes, LDPC-layered decoding.1549-8328

An Area-efficient Half-row Pipelined Layered LDPC Decoder Architecture

“…The corresponding area efficiency of the proposed work is 76.81 Mbps/mm 2 , whereas the area efficiency obtained by Li et al [11], Park et al [18], Kumawat et al [19], and Lee et al [20] Table 2, it can be concluded that the proposed work is the most area-efficient among the reported LDPC decoders. Although the design from Lee et al [20] achieves the highest data rate (10.97 Gbps at 10 iterations), it suffers from a larger chip core area, compared to our proposed design.…”

“…The submatrix size, z, is set to 42 for IEEE 802.11ad, to 81 for IEEE 802.11n, and to 21 for IEEE 802.15.3c applications. First of all, analysis results show that the proposed halfrow pipelined layered LDPC decoder reduces the complexity of nearly all components by half, compared to the fully parallel pipelined layer LDPC decoder design of Kumawat et al [19]. Moreover, the proposed decoder reduces the major area-consuming components, like adders, sign magnitude conversion (SMC), and min comparators, compared to flooding decoders [18,20].…”

Hardware-Efficient Node Processing Unit Architectures for Flexible LDPC Decoder Implementations

“…Accordingly, the specific implementation characteristics of NPUs having the proposed dual-tree architecture depend on the characteristics of these subnodes. In order to facilitate a comparison and discussion in this section, we consider NPUs having subnodes which calculate the min (x, y) of two 4-bit unsigned inputs x and y, as used within fixed-point CNPUs performing the MSA 1 [14]. Since this function is non-invertible, the single binary tree structure mentioned in Section I is not viable.…”

“…Alternatively, parallel flexible NPUs may be implemented having the maximum number of inputs and outputs, namely I = D C for CNPUs or I = D V + 1 for VNPUs, where D C and D V refer to the maximum values of d c and d v within the set of supported PCMs, respectively. When used for processing nodes having lower degrees, the unused inputs may be effectively disabled by supplying them with a "null" value [12]- [14]. For the example of VNPUs processing messages in the form of binary fixed-point Logarithmic-Likelihood Ratios (LLRs), each subnode performs the addition of two LLRs.…”

“…Alternative architectures must therefore be employed when the subnode operation is not invertible, as is the case with the min operation of CNPUs performing the Min-Sum Algorithm (MSA), for example [14]. One rudimentary option, henceforth referred to as a multi-tree architecture, is to use I parallel binary trees to calculate the combination of each of the I possible sets of I − 1 inputs [12].…”