High throughput hardware design for the Adaptive Loop Filter of the emerging HEVC video coding

Rediess, Fabiane; Agostini, Luciano; Cristani, Cassio; Dall'Oglio, Pargles; Porto, Marcelo

doi:10.1109/sbcci.2012.6344446

Cited by 10 publications

(7 citation statements)

References 2 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…study for the ALF hardware implementation and discusses the most challenging part which is the memory. Like the work of [21,22], a shared architecture is proposed for multiple filters taking advantage of the fact that smaller filters are nested within larger ones by using a number of regular multipliers.…”

Section: Discussionmentioning

confidence: 99%

“…The work in [21] was synthesized targeting an FPGA platforms of 40 nm technology. Fabiane et al [22] proposed efficient hardware designs for the ALF cores of sizes 5×5, 7×7 and 9×9. Similar to [21], the symmetrical feature of the ALF is explored to reduce the total number of multipliers.…”

Section: Related Workmentioning

confidence: 99%

“…Results showed that the proposed designs were able to process 110, 102 and 98 frames per second in 1080p resolution for the 5 × 5, 7 × 7 and 9 × 9 filter sizes, respectively. In [23], the same author presented a hardware architecture for the 5 × 5 ALF core targeting the same family of FPGA platforms.…”

Section: Related Workmentioning

confidence: 99%

“…The solutions proposed in [21][22][23] discuss only the calculation part of ALF filters and do not address the memory. Unlike these solution, our solution provides a complete…”

Section: Comparison With State-of-the-artmentioning

confidence: 99%

See 3 more Smart Citations

Adaptive Loop Filter Hardware Design for 4K ASIC VVC Decoders

Farhat

Hamidouche

Grill

et al. 2022

IEEE Trans. Consumer Electron.

View full text Add to dashboard Cite

Versatile video coding (VVC) is the next generation video coding standard released in July 2020. VVC introduces new coding tools enhancing the coding efficiency compared to its predecessor high efficiency video coding (HEVC). These new tools have a significant impact on the VVC software decoder with a complexity estimated to two times HEVC decoder complexity. In particular, the adaptive loop filter (ALF) introduced in VVC as an in-loop filter increases both the decoding complexity and memory usage. These concerns need to be carefully addressed regarding the design of an efficient hardware implementation of a VVC decoder. In this paper, we present an efficient hardware implementation of the ALF tool for VVC decoder. The proposed solution establishes a novel scanning order between Luma and Chroma components that reduces significantly the ALF memory. The design takes advantage of all ALF features and establishes an unified hardware module for all ALF filters. The design uses 26 regular multipliers in a pipelined architecture with a fixed throughput of 2 pixels/cycle and fixed system latency regardless of the selected filter. This design operates at 600 MHz frequency enabling to decode on ASIC platform a 4K video at 30 frames per second in 4:2:2 chroma sub-sampling format.

show abstract

Section: Discussionmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

Section: Related Workmentioning

confidence: 99%

“…The solutions proposed in [21][22][23] discuss only the calculation part of ALF filters and do not address the memory. Unlike these solution, our solution provides a complete…”

Section: Comparison With State-of-the-artmentioning

confidence: 99%

See 2 more Smart Citations

Adaptive Loop Filter Hardware Design for 4K ASIC VVC Decoders

Farhat

Hamidouche

Grill

et al. 2022

IEEE Trans. Consumer Electron.

View full text Add to dashboard Cite

show abstract

“…The architecture uses 9×9 tap ALF and can process a macroblock in 843 clock cycles. The maximum clock frequency of the architecture is 211 MHz.Radiess et al[10] have designed a hardware implementation for ALF filtering based on the Test Model HM-4.0 of the HEVC standard. Since HM-4.0 includes three different filter shapes (diamond 5×5, 7×7 and 9×9), three hardware architectures are proposed.…”

mentioning

confidence: 99%

Programmable lowpower implementation of the HEVC Adaptive Loop Filter

Hautala

Boutellier

Hannuksela

2013

2013 IEEE International Conference on Acoustics, Speech and Signal Processing

View full text Add to dashboard Cite

The Adaptive Loop Filter (ALF) is a subjective and objective image quality improving filter in the High Efficiency Video Coding standard (HEVC). The ALF has shown to be computationally complex and its complexity has been reduced during the HEVC development process. In the HEVC Test Model HM-7.0 ALF is a 9×7 cross + 3×3 square shaped filter.This paper presents a programmable application specific instruction processor for the ALF. The proposed processor processes 1920×1080p luminance frames at 30 frames per second, when operated at a clock frequency of 311 MHz. Low power consumption and a low gate count make the proposed processor suitable for embedded devices. The processor program code is written in pure C-language, which allows versatile use of the circuit and updates to the filter functionality without modifying the processor design. To the authors' best knowledge this is the first programmable solution for ALF on embedded devices.

show abstract