High-Throughput DNN Inference with LogicNets

Umuroglu, Yaman; Akhauri, Yash; Fraser, Nicholas J.; Blott, Michaela

doi:10.1109/fccm48280.2020.00071

Cited by 3 publications

(2 citation statements)

References 2 publications

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“…Therefore the depth of the network remains unchanged. Other task-specific neural network frameworks optimized for FPGA mapping include LUTnet [11] and LogicNets [12]. These frameworks advance the concept of using the FPGA LUTs to implement 2-input XNORs between weights and activations, as used in binary networks, in order to exploit the capabilities of the multi-input LUTs.…”

Section: Model-specific Neural Architecturesmentioning

confidence: 99%

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Nunez-Yanez

Otero

Torre

2023

Microprocessors and Microsystems

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Section: Model-specific Neural Architecturesmentioning

confidence: 99%

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Nunez-Yanez

Otero

Torre

2023

Microprocessors and Microsystems

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“…DNNs designed and trained in this manner result in fast and efficient FPGA implementations that can fulfill the performance requirements for extreme-throughput applications. Extending on our abstract in [8], this paper makes the following contributions:…”

Section: Introductionmentioning

confidence: 97%

LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

Umuroglu

Akhauri

Fraser

et al. 2020

2020 30th International Conference on Field-Programmable Logic and Applications (FPL)

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Deployment of deep neural networks for applications that require very high throughput or extremely low latency is a severe computational challenge, further exacerbated by inefficiencies in mapping the computation to hardware. We present a novel method for designing neural network topologies that directly map to a highly efficient FPGA implementation. By exploiting the equivalence of artificial neurons with quantized inputs/outputs and truth tables, we can train quantized neural networks that can be directly converted to a netlist of truth tables, and subsequently deployed as a highly pipelinable, massively parallel FPGA circuit. However, the neural network topology requires careful consideration since the hardware cost of truth tables grows exponentially with neuron fan-in. To obtain smaller networks where the whole netlist can be placed-and-routed onto a single FPGA, we derive a fan-in driven hardware cost model to guide topology design, and combine high sparsity with low-bit activation quantization to limit the neuron fan-in. We evaluate our approach on two tasks with very high intrinsic throughput requirements in high-energy physics and network intrusion detection. We show that the combination of sparsity and low-bit activation quantization results in high-speed circuits with small logic depth and low LUT cost, demonstrating competitive accuracy with less than 15 ns of inference latency and throughput in the hundreds of millions of inferences per second.

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NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs

Wang

Rai

Ullah

et al. 2023

2023 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW)

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High-Throughput DNN Inference with LogicNets

Cited by 3 publications

References 2 publications

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

Dynamically reconfigurable variable-precision sparse-dense matrix acceleration in Tensorflow Lite

LogicNets: Co-Designed Neural Networks and Circuits for Extreme-Throughput Applications

NetPU-M: a Generic Reconfigurable Neural Network Accelerator Architecture for MLPs

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