High-temperature performance of MoS2 thin-film transistors: Direct current and pulse current-voltage characteristics

Abstract

The measurements of the high-temperature current-voltage characteristics of MoS 2 thinfilm transistors show that the devices remain functional to temperatures of at least as high as 500 K. The temperature increase results in decreased threshold voltage and mobility.The comparison of the DC and pulse measurements shows that the DC sub-linear and super-linear output characteristics of MoS 2 thin-films devices result from the Joule heating and the interplay of the threshold voltage and mobility temperature dependences. At temperatures above 450 K, an intriguing phenomenon of the "memory step" -a kink in the drain current -occurs at zero gate voltage irrespective of the threshold voltage value. The memory step effect was attributed to the slow relaxation processes in thin films similar to those in graphene and electron glasses. The obtained results suggest new applications for MoS 2 thin-film transistors in extreme-temperature electronics and sensors.

Impact of contact resistance on the electrical properties of MoS2 transistors at practical operating temperatures

“…A temperature range from room temperature to 400 K is a realistic range for device operation in circuits/systems, taking into account the heating effect they undergo due to inefficient heat dissipation. However, to date, only a limited number of papers have focused on the high temperature behavior of MoS 2 transistors [ 8 – 9 ].…”

Quantitative Analysis of Scattering Mechanisms in Highly Crystalline CVD MoS2through a Self-Limited Growth Strategy by Interface Engineering

“…[ 2 ] Interestingly, in the higher temperature region (350-400 K, limited by organic OTMS-SAM), the mobility severely decreases with increasing temperature, which could be assigned to a contribution of a higher interface trap density. [ 44 ] The material parameters used in our calculations are adopted from the previously reported values [ 18,20 ] and listed in Table S1 (Supporting Information). To illustrate the spatial distributions of the dominated scattering via Coulomb potential due to the CI, we consider two separated CI located both inside ( Figure 4 a) and outside (Figure 4 b) the MoS 2 layer, by considering our device dielectric environment and measured thickness ( t ≈ 1.1 nm) of monolayer MoS 2 by AFM.…”

1/<inline-formula> <tex-math notation="LaTeX">$f$ </tex-math></inline-formula> Noise Characteristics of MoS₂ Thin-Film Transistors: Comparison of Single and Multilayer Structures

“…Thin films of MoS 2 were prepared by a standard exfoliation method and placed on Si/SiO 2 substrates. Details of material preparation can be found in [17] and references therein. The thickness and quality of thin films were determined with the atomic force microscopy (AFM) and micro-Raman spectroscopy.…”