High‐Temperature Operation of Al_xGa_1−xN (x > 0.4) Channel Metal Oxide Semiconductor Heterostructure Field Effect Transistors with High‐k Atomic Layer Deposited Gate Oxides

Abstract

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Threshold voltage control with high-temperature gate-oxide annealing in ultrawide bandgap AlGaN-channel MOSHFETs

“…In the past, we studied the electron mobility of ultrawide bandgap HFETs and MOS-HFETs with different high-k dielectric layers. 26) Although the mobility temperature dependencies differed for HFET and MOSHFETs, the typical mobility range was the same for both device types. In this work, we used two-step PDA, which we believe is the main difference leading to mobility enhancement.…”

“…High-k ALD oxides have already shown superior device performance in UWBG MOSHFETs. 25,26) In this report we present an oxide thickness (t ox ) dependent study of V TH values for MOSHFETs with annealed and unannealed high-k ALD ZrO 2 gate-insulator to separate the contributions from n ox,bulk and n .…”

High-current recessed gate enhancement-mode ultrawide bandgap Al x Ga1−x N channel MOSHFET with drain current 0.48 A mm−1 and threshold voltage +3.6 V

“…s −1 at V G +12 V, consistent with past reports. 38) Figure 3(a) compares the semi-log transfer characteristics for the device of Fig. 2(a) measured at V DS = +20 V with that for an identical geometry D-mode device (no gate-recess) fabricated on the same wafer, showing a V TH shift of +12.2 V due to the gate recess.…”

Ultrawide bandgap Al x Ga1–x N channel heterostructure field transistors with drain currents exceeding 1.3 A mm−1

“…Details of ALD process are described in. 25) Identical geometry HFET and MOSHFET devices both with the (CC) and the (PC) layout were fabricated on the same epi-wafer for a comparative study. The transistor surface was also protected with PECVD deposited 400 nm SiO 2 film for high voltage measurements.…”

“…The threshold voltage Vth = −11 V was the same for both the CC and the PC layouts and was not affected by introduction of additional epi-layers compared to previously reported results. 20,23,25) Relative contributions of the three key features employed in current design, namely-(1) reverse graded barrier layer, (2) perforated channel layout and (3) MOS-gate designtowards maximum drain current are shown in Fig. 3(a).…”