P b -type interface defects in (100) Si/SiO 2 structures grown in ozonated water solutionElectron spin resonance studies have been carried out on the isothermal passivation kinetics in 1 atm molecular H 2 of trivalent Si traps (P b s;Si 3 wSi • ͒ at the interface of thermal (111)/Si/SiO 2 as a function of oxidation temperature T ox in the range 250-1100°C. Interpretation within the generalized simple thermal ͑GST͒ passivation model, based on first-order interaction kinetics, reveals a distinct increase in spread E f in the activation energy for passivation E f with decreasing T ox ͑ϳ3 times in the covered T ox window͒, while the other key kinetic parameters ͑E f , preexponential factor͒ remain essentially unchanged. The variation in E f is ascribed to differently relaxed interfacial stress, affecting the spread in P b defect morphology. In a second analytic part, the impact of the variation in E f , and correlatively in the activation energy E d for P b H dissociation, on P b -hydrogen interaction kinetics is assessed within the GST-based full interaction scheme, describing parallel competing action of passivation and dissociation. In particular, the passivation behavior in 1 atm H 2 of an initially exhaustively depassivated P b system, is analyzed exposing, as a major result, that growing spreads E f , E d result in a drastic reduction in passivation efficiency ͑drop by four orders of magnitude for a threefold increase in E f ͒. For E f /E f տ20%, the P b system cannot be inactivated beyond the 90% level, incompatible with device quality requirements. Heating time/temperature vs spread conditions for optimum passivation in H 2 have been established, and the technological impact of altering E f , E d is discussed. At film edges and trench corners, which are vulnerable local regions of exces stress, and hence enhanced E f , E d , an edge defeat effect with respect to passivation is exposed. Within the relentless scaling of Si-based integrated circuit devices, the growing relative impact of edge regions may jeopardize proper passivation of interface traps in the conventional way in future device generations.