High temperature alternatives to ball grid coplanarity measurements to improve correlation to surface mount quality

Gamer, L.; Raghavan, P.; Noolu, N.J.; Sánchez, Jorge; Lee, Yung Hsiang

doi:10.1109/ectc.2008.4550003

Cited by 7 publications

(3 citation statements)

References 2 publications

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“…In addition, warpage is a function of temperature so the warpage shape and magnitude may not match room temperature measurement as shown in an example illustrated in Figure 9. Characterizing warpage vs. temperature is important to ensure good interconnect yield and reliability in additional to reduce room temperature warpage and collect SMT yield data [21][22][23]. A reflow temperature flatness requirements spec is released by JEDEC as an alternative to room temperature warpage requirements [24].…”

Section: Warpage and Its Impact To Yield And Reliabilitymentioning

confidence: 99%

Quality and reliability challenges for ultra mobile computing and communication application processor packaging

Kang

2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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Market drivers, technology scaling and integration trends of application processor packaging are first presented. Component level and board level quality and reliability challenges are then discussed in the areas of thin die and thin core package warpage, lead free flip chip die to package interconnect mechanical integrity, and lead free package to motherboard solder joint reliability. Challenges from package qualification methodology and use condition are also addressed.

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Section: Warpage and Its Impact To Yield And Reliabilitymentioning

confidence: 99%

Quality and reliability challenges for ultra mobile computing and communication application processor packaging

Kang

2009

2009 International Conference on Electronic Packaging Technology &Amp; High Density Packaging

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“…During the last years however it was found that at least for BGA type packages the warpage at reflow temperature is also a critical parameter for a robust SMT process [1]. Warpage at room and reflow temperature is typically significantly different because of the thermomechanical properties of package materials.…”

Section: Introductionmentioning

confidence: 99%

Warpage measurements of laminate based BGA packages at elevated temperatures and comparison with real board assembly behaviour

Birzer

Graml

Dittes

et al. 2008

2008 33rd IEEE/CPMT International Electronics Manufacturing Technology Conference (IEMT)

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This paper is about warpage of laminate substrate based BGAs and fine pitch BGAs at lead-free board assembly reflow temperatures using shadow moiré technique. Various constructions (e.g. single die devices and multi chip modules) and different die and package sizes as well as different molding compound materials were considered in this study. A simple model for predicting high temperature warpage for single die devices based on the distance between package corner and die corner was developed. The comparison of the warpage results with and without moisture soaking according JEDEC MSL 3 did not exhibit a significant influence on high temperature warpage. The shadow moiré test results at elevated temperatures are compared with solder joint height distributions measured in cross sections after real lead-free board assembly. A clear correlation of the solder joint height distributions with the package warpage status at 170 °C during cooling phase was found. This is much lower than the mominal solidification temperature of lead-free solder. This study helps to understand the influencing factors of BGA warpage and its role for board assembly.

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“…Among many, package warpage characteristic has been the industry wide common focus. The introduction of a JEDEC's reflow temperature warpage specification [5] gives more realistic assessment to component board assembly yield compared to room temperature coplanarity as demonstrated in [6]. Based on JIETA specification [7] and experimental work from Cho and Amir et.al.…”

Section: Introductionmentioning

confidence: 99%

Package-on-Package (PoP) warpage characteristic and requirement

Loh

Kulterman

Purdie³

et al. 2015

2015 IEEE 17th Electronics Packaging and Technology Conference (EPTC)

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Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging. The warpage characterization also extended to evaluate the effect of bake and Moisture Exposure Time (MET) on package dynamic warpage. These will provide a better holistic view of cause and effect in PoP package stacking. Keywords-dynamic warpage; Package-on Package (PoP).

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High temperature alternatives to ball grid coplanarity measurements to improve correlation to surface mount quality

Cited by 7 publications

References 2 publications

Quality and reliability challenges for ultra mobile computing and communication application processor packaging

Quality and reliability challenges for ultra mobile computing and communication application processor packaging

Warpage measurements of laminate based BGA packages at elevated temperatures and comparison with real board assembly behaviour

Package-on-Package (PoP) warpage characteristic and requirement

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