High-speed ΣΔ modulators with reduced timing jitter sensitivity

Luschas, S.; Lee, Hae-Seung

doi:10.1109/tcsii.2002.807575

Cited by 56 publications

(28 citation statements)

References 3 publications

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“…Another reported technique to reduce clock jitter effects explores the use of sin-shaped DAC feedback [22,23] (an example of its waveform is also shown in Figure 2). In this technique, clock transitions take place when the sin-shaped feedback is at its maximum slope and hence results in a small charge error.…”

Section: Review Of Previous Workmentioning

confidence: 99%

“…But for sin-shaped DAC feedback, the circuit realization based on phase-locked loop is complex and difficult and it may dramatically increase power consumption. In addition, it is sensitive to loop delay, locking error and phase/amplitude noise of the feedback pulse itself [22,23]. Besides, extensibility of the sin-shaped DAC feedback to multi-bit operation is poor [7].…”

Section: Review Of Previous Workmentioning

confidence: 99%

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Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

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Abstract:It is well known that continuous-time Delta-Sigma modulators are very sensitive to clock jitter effects. In literature, a number of techniques have been proposed to cope with them. In this brief, we present a detailed review and comparison of the reported techniques. While the effectiveness to reduce clock jitter effects may be of most importance in this comparison, we also consider other performance metrics such as circuit complexity and overhead to implement the technique, power consumption overhead of technique, synthesis complexity incurred in system-level design, extensibility of the technique from single-bit to multi-bit operation, and robustness to process variation. When clock jitter is relatively large, the fixed-width pulse feedback technique is most effective to reduce clock jitter effects among all techniques at high sampling frequency, while switched-capacitor-resistor and switched-shaped current techniques have best performance at medium frequency or below.

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Section: Review Of Previous Workmentioning

confidence: 99%

Section: Review Of Previous Workmentioning

confidence: 99%

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Chang

Tang

2017

JLPEA

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“…This chapter will explore the sources of error in the RF DAC system, including locking error, phase and amplitude noise [27]. The phase and amplitude noise will be compared both intuitively and analytically between the square waveform and the oscillating waveform.…”

mentioning

confidence: 99%

Radio frequency digital-to-analog converter

Luschas¹,

Schreier

Lee

2004

IEEE J. Solid-State Circuits

Self Cite

114

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Dynamic performance of high speed, high resolution digital-to-analog converters (DACs) is limited by distortion at the data switching instants. Inter-symbol interference (ISI), imperfect timing synchronization and clock jitter are all culprits. A DAC output current controlled by an oscillating waveform is proposed to mitigate the effects of the switching distortion. The oscillating waveform should be a multiple (k*fs) of the sampling frequency (fs), where k>1. The waveforms can be aligned so that the data switching occurs in the zero regions of the oscillating output. This makes the DAC insensitive to switch dynamics and jitter. The architecture has the additional benefit of mixing the DAC impulse response energy to a higher frequency. An image of a low IF input signal can therefore be output directly at a high IF or RF frequency for transmit communications applications. A narrowband sigma-delta DAC with eight unit elements is chosen to demonstrate the radio frequency digital-to-analog converter (RF DAC) concept. A sigma-delta architecture allows the current source transistors to be smaller since mismatch shaping is employed. Smaller current source transistors have a lower drain capacitance, allowing large high frequency output impedance to be achieved without an extra cascode transistor. Elimination of the cascode reduces transistor headroom requirements and allows the DAC to be built with a 1.8V supply. The RF DAC prototype is targeted to GSM transmit specifications and implemented in 0.1 8ptm CMOS technology. Measured single-tone SFDR is -75dBc, SNR is 52dB, and IMD3 is -70.8dBc over a 17.5MHz bandwidth centered at 942.5MHz. Measured SNR has the predicted dependence on the phase alignment of the data clock and oscillating pulse.

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“…We notice that when the excess loop delay is greater than 1 sampling period, the compensation transfer function, equation (6), does not cancel all the undesired terms of the equation (5). Therefore, we have to increase the order of the useful FIRDAC to cancel these terms by using its coefficients u i :…”

Section: Calculation Of Firdac Coefficientsmentioning

confidence: 99%

“…At RF frequencies, this would significantly increase the sampling frequency, f S = 4f o , and would consequently increase the complexity and power consumption of the Σ∆ modulator and the subsequent digital circuits. Clock jitter is also a serious source of SNR degradation at high sampling frequencies [5].…”

Section: Introductionmentioning

confidence: 99%

Undersampled LC Bandpass ΣΔ Modulators with Feedback FIRDACs

Kammoun¹,

Beilleau²,

Aboushady³

2006 IEEE International Symposium on Circuits and Systems

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Abstract-A general technique for the design of undersampled LC bandpass modulators using feedback FIRDACs is proposed. The coefficients of the FIRDACs are used to increase the degrees of freedom in order to perform an exact equivalence between undersampled LC bandpass Sigma-Delta and high order DiscreteTime Sigma-Delta modulators. Using FIRDACs coefficients, it is also possible to simplify the circuit implementation by removing internal summing nodes and by decreasing coefficients spread. An undersampled 4th order LC Sigma-Delta is given as a design example. The effect of the undersampling ratio on the performance of finite quality factor LC Sigma-Delta modulators is also studied.

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High-speed ΣΔ modulators with reduced timing jitter sensitivity

Cited by 56 publications

References 3 publications

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Review and Comparison of Clock Jitter Noise Reduction Techniques for Lowpass Continuous-Time Delta-Sigma Modulators

Radio frequency digital-to-analog converter

Undersampled LC Bandpass ΣΔ Modulators with Feedback FIRDACs

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