High speed pattern matching for a fast Huffman decoder

Choi, Seung Bae; Lee, Moon Ho

doi:10.1109/30.370315

Cited by 41 publications

(4 citation statements)

References 10 publications

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“…A simple strategy to find is using iterative bisection search algorithm [16] which makes toward . Furthermore, since each is independent of , to solve (9) is equivalent to solve (10) That is, we can separately find which minimizes (11) under the given . With the aid of the P-R cost function, the join penalty-resource optimal solution for an HDM with multiple HTs can be found systematically.…”

Section: Lagrangian Multiplier Optimizationmentioning

confidence: 99%

“…We first introduce two partition methods to cluster an HT into several LUTs: the modified Hashemian cut (MHC) and the bits-pattern-Xor (Bpx). These two methods are motivated by the Hashemian's method [7] and the bits-pattern matching scheme [9], [10], respectively. Hahemian's method [7] uses fixed length clustering and a supper tree to memories the location of individual subtree.…”

Section: Hierarchical Arbitrary-side Growing Table (Hasgt)mentioning

confidence: 99%

“…MHC behaves very similar to Hahemian's method except the length of clusters is varying, and also incorporates a supper tree into LUTs. The scheme given in [9], [10] simply counts the leading 1's of symbols, so it is inefficient for an AGH-tree; therefore, a better memory usage can be expected. Bpx is a LUT that indexes each symbol by the number of leading common bits with a certain bits-pattern (cf.…”

Section: Hierarchical Arbitrary-side Growing Table (Hasgt)mentioning

confidence: 99%

“…This multiple-bit-inspecting nature implies that the LUT-based method needs shorter memory access time than that of the tree-based apporach, in general. Hashemian, in [7], partitioned an HT by clustering several bits together into subtrees and constructed a memory efficient LUT for each subtree; Aggarwal et al [8] partitioned the code symbols into clusters and constructed one LUT for each cluster; Choi et al [9] and Jiang et al [10] partitioned an SGH-tree on the basis of pattern-matching and constructed memory-efficient LUT-based Huffman decoders. In general, when an HT is irregularly sparse, the approaches of [7]- [10] will face the memory waste problem because there are many redundant nodes (i.e., redundant table entries).…”

Section: Introductionmentioning

confidence: 99%

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Memory Efficient Hierarchical Lookup Tables for Mass Arbitrary-Side Growing Huffman Trees Decoding

Wang

Chuang

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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This paper addresses the optimization problem of minimizing the number of memory access subject to a rate constraint for any Huffman decoding of various standard codecs. We propose a Lagrangian multiplier based penalty-resource metric to be the targeting cost function. To the best of our knowledge, there is few related discussion, in the literature, on providing a criterion to judge the approaches of entropy decoding under resource constraint. The existing approaches which dealt with the decoding of the single-side growing Huffman tree may not be memory-efficient for arbitrary-side growing Huffman trees adopted in current codecs. By grouping the common prefix part of a Huffman tree, in stead of the commonly used single-side growing Huffman tree, we provide a memory efficient hierarchical lookup table to speed up the Huffman decoding. Simulation results show that the proposed hierarchical table outperforms previous methods. A Viterbi-like algorithm is also proposed to efficiently find the optimal hierarchical table. More importantly, the Viterbi-like algorithm obtains the same results as that of the brute-force search algorithm.

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Section: Lagrangian Multiplier Optimizationmentioning

confidence: 99%

Section: Hierarchical Arbitrary-side Growing Table (Hasgt)mentioning

confidence: 99%

Section: Hierarchical Arbitrary-side Growing Table (Hasgt)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Memory Efficient Hierarchical Lookup Tables for Mass Arbitrary-Side Growing Huffman Trees Decoding

Wang

Chuang

et al. 2008

IEEE Trans. Circuits Syst. Video Technol.

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A Reconfigurable Functional Unit for TriMedia/CPU64. A Case Study

Sima

Cotöfană

Vassiliadis

et al. 2002

Embedded Processor Design Challenges

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Abstract. The paper presents a case study on augmenting a TriMedia/CPU64 processor with a Reconfigurable (FPGA-based) Functional Unit (RFU). We first propose an extension of the TriMedia/CPU64 architecture, which consists of a RFU and its associated instructions. Then, we address the computation of the ¢ IDCT on such extended TriMedia, and propose a scheme to implement an 8-point IDCT operation on the RFU. Further, we address the decoding of Variable Length Codes and describe the FPGA implementation of a Variable Length Decoder (VLD) computing facility. When mapped on an ACEX EP1K100 FPGA from Altera, our 8-point IDCT exhibits a latency of 16 and a recovery of 2 TriMedia cycles, and occupies 42% of the FPGA's logic array blocks. The proposed VLD exhibits a latency of 7 TriMedia cycles when mapped on the same FPGA, and utilizes 6 of its embedded array blocks. By using the 8-point IDCT computing facility, an ¢ IDCT including all overheads can be computed with the throughput of 1/32 IDCT/cycle. Also, with the proposed VLD computing facility, a single DCT coefficient can be decoded in 11 cycles including all overheads. Simulation results indicate that by configuring each of the 8-point IDCT and VLD computing facilities on a different FPGA context, and by activating the contexts as needed, the augmented TriMedia can perform MPEG macroblock parsing followed up by a pel reconstruction with an improvement of 20-25% over the standard TriMedia.

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