High speed networking at Cray research

Nicholson, Andy; Golio, Joe; Borman, David A.; Young, Jeff; Roiger, Wayne

doi:10.1145/116030.116038

Cited by 16 publications

(7 citation statements)

References 3 publications

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“…The figures give only an idea on the possible performance of XTP when implemented in the user level. Other detailed performance tests can be found in [Cab88] and [Nic91] for TCP and in [Fan93] for XTP. A user level implementation of protocol of TCP is described in [The93].…”

Section: Performance Testsmentioning

confidence: 99%

High performance presentation and transport mechanisms for integrated communication subsystems

Dabbous

1995

IFIP Advances in Information and Communication Technology

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The performance enhancement of communication protocols is an essential step toward the building of high performance communication subsystems. Integrated Layer Processing (ILP) has been proposed as an engineering principle for the optimization of communication protocol implementations. However, the applicability of this principle to complete operational communication subsystems has not been yet addressed. This is in part due to the lack of high performance implementation of presentation and transport functions. In this paper, we show to what extent "ILP based" optimizations improve the performance of some data manipulation functions (e.g. presentation encoding or checksumming) independently. We present how some of these implementation optimization techniques were applied to the ASN.l encodings rules. We also analyze the impact of such optimization techniques according to the support hardware. A prototype implementation of the XTP protocol is also described. ILP based optimization applied to the checksum calculation algorithm show that an important performance enhancement can be achieved. These results should facilitate the support of ILP within an operational communication subsystem.

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Section: Performance Testsmentioning

confidence: 99%

High performance presentation and transport mechanisms for integrated communication subsystems

Dabbous

1995

IFIP Advances in Information and Communication Technology

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“…Thinking is a processing bottleneck, exhibited in the processing speed ofTCPIIP and the operating system (OS) interface involved in the transaction. The processing bottleneck for TCP has been addressed by parallelism [16], [1] (both discussed later), even though its performance has been shown not to be the predominant limitation to communication [17], [10]. Other components of the protocol stack have also been parallelized, e.g., via pipelining of the IP check-sum with the data transfer [5].…”

Section: What's the Problem?mentioning

confidence: 99%

“…One interesting question assumes nearly instantaneous thinking (protoco processing) and answering (bandwidth), and asks, "is there anything else?" Presume that TCP has infinite window sizes, and can run at 800 Mbps (it can on a CRAY [17]). Presume that we have a NetStation, in which each component of a workstation (disk, RAM, display, etc., [7]) can both source and sink at 800 Mbps.…”

Section: What's the Problem?mentioning

confidence: 99%

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Protocol Parallelization

Touch¹

1995

IFIP Advances in Information and Communication Technology

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There is increasing concern about the capability of existing protocols to keep pace with communication rates, as rates approach the gigabit range. This assumes a sort of "protocol bottleneck." Many similar bottlenecks are alleviated by the use of parallelism, so one hypothesis is to "parallelize" protocols. We examine the pros and cons of this hypothesis, and the dimensions to which parallelism might be applied. We distinguish the unique communication issues that result. Our conclusions indicate that conventional parallelism may not be applicable to protocols. New types of parallelism become more significant in this light. These include information parallelism (Parallel Communication) and packet-train parallelism.

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“…The reason is that they are inherently scalable, and provide relatively inexpensive computing cycles compared with traditional uniprocessor or shared-memory multiprocessor supercomputers. However, while traditional sequential or shared-memory supercomputers such as the Cray have been able to make good use of the HIPPI bandwidth [16], distributed-memory machines have been much less successful. The network interfaces of distributed-memory machines often have low sustained bandwidth, do not perform network protocol processing, or manage connections inefficiently.…”

Section: Introductionmentioning

confidence: 99%

Architecture and evaluation of a high-speed networking subsystem for distributed-memory systems

Steenkiste¹,

Hemy²,

Mummert³

et al.

Proceedings of 21 International Symposium on Computer Architecture

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Achieving high-speed network U0 on distributed-memory systems is difficult because their architecture is in general ill-suited for communication processing. Some of the common problems are: inability to do protocol processing, inefficient handling of data distribution, and poor management of the I/O. In this paper we present an 110 architecture that addresses these problems and supports high-speed network I/O on distributed-memory systems. The key to good performance is to partition the work appropriately between the system and the network interface. We perform some communication tasks on the distributed-memory parallel system since it is more powerful, and less likely to become a bottleneck than the network interface. Tasks that do not parallelize well are performed on the network interface and hardware support is provided for the most time-critical operations. We emphasize the use of simple I/O mechanisms that can be used by programming tools that map applications on the distributed-memory system to implement efficient YO for the class of applications they support. This architecture has been implemented for the iWarp distributed-memory system.We describe this implementation and present performance results. 154 1063-6897/94 $03.00 0 1994 IEEE 3. iWarp overview iWarp is a distributed-memory parallel computing system [2]. An iWarp cell consists of a single-chip iWarp processor and a local memory. The iWarp processor integrates both a high-speed computation and communication agent in a single component. The communication agent connect the iWarp cell to four neighbors through 40 MByte/second buses; the cells in the iWarp array are configured as a torus. The communication system supports high-speed interprocessor communication for a variety of communication models, including systolic communication and memory communication (e.g. conventional message passing as found in distributed memory machines) [3].Memory communication is supported through the use of DMA-like engines that move data between the local memory and the interconnection network.

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High speed networking at Cray research

Cited by 16 publications

References 3 publications

High performance presentation and transport mechanisms for integrated communication subsystems

High performance presentation and transport mechanisms for integrated communication subsystems

Protocol Parallelization

Architecture and evaluation of a high-speed networking subsystem for distributed-memory systems

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