Architecture and evaluation of a high-speed networking subsystem for distributed-memory systems

Abstract

Achieving high-speed network U0 on distributed-memory systems is difficult because their architecture is in general ill-suited for communication processing. Some of the common problems are: inability to do protocol processing, inefficient handling of data distribution, and poor management of the I/O. In this paper we present an 110 architecture that addresses these problems and supports high-speed network I/O on distributed-memory systems. The key to good performance is to partition the work appropriately between the system and the network interface. We perform some communication tasks on the distributed-memory parallel system since it is more powerful, and less likely to become a bottleneck than the network interface. Tasks that do not parallelize well are performed on the network interface and hardware support is provided for the most time-critical operations. We emphasize the use of simple I/O mechanisms that can be used by programming tools that map applications on the distributed-memory system to implement efficient YO for the class of applications they support. This architecture has been implemented for the iWarp distributed-memory system.We describe this implementation and present performance results. 154 1063-6897/94 $03.00 0 1994 IEEE 3. iWarp overview iWarp is a distributed-memory parallel computing system [2]. An iWarp cell consists of a single-chip iWarp processor and a local memory. The iWarp processor integrates both a high-speed computation and communication agent in a single component. The communication agent connect the iWarp cell to four neighbors through 40 MByte/second buses; the cells in the iWarp array are configured as a torus. The communication system supports high-speed interprocessor communication for a variety of communication models, including systolic communication and memory communication (e.g. conventional message passing as found in distributed memory machines) [3].Memory communication is supported through the use of DMA-like engines that move data between the local memory and the interconnection network.

Gigabit Nectar: Architecture and Performance.

“…In the iWarp HIPPI interface [45], these problems are addressed by mapping each task onto the subsystem that is the most appropriate for it (network interface or distributed memory system):…”