High-speed multi-modulus prescaler IC

Kamoto, T.; Adachi, Nobuo; Yamashita, K.

doi:10.1109/icupc.1995.496914

Cited by 10 publications

(6 citation statements)

References 2 publications

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“…This stems from its interface with the highest frequency in the system. A lot of architectures have been proposed for high-speed operation as in [1]- [4]. In both [1] and [2], the proposed architecture is programmable, dynamically loadable and suitable for high-speed operation.…”

Section: Introductionmentioning

confidence: 99%

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Extended division range 2/3 chain frequency divider with dynamic control word

Ashour¹,

Dessouky

Sharaf

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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This paper presents a 4-31 programmable frequency divider with dynamic control word built in 90 nm CMOS. The divider uses a chain of 2/3 dual modulus pre-scalar cells. This paper presents a modification to the conventional 2/3 dual modulus pre-scalar building cell. This modification allows changing the control word dynamically during the operation. The divider consists of a chain of four 2/3 dual modulus cells. The maximum operating frequency is 7.9 GHz consuming 24.5 mA at a low voltage supply of 1V.

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Section: Introductionmentioning

confidence: 99%

“…A lot of architectures have been proposed for high-speed operation as in [1]- [4]. In both [1] and [2], the proposed architecture is programmable, dynamically loadable and suitable for high-speed operation. However, the division range is limited from 2 N to 2 N +1 -1, where N is the number of stages in the divider chain.…”

Section: Introductionmentioning

confidence: 99%

Extended division range 2/3 chain frequency divider with dynamic control word

Ashour¹,

Dessouky

Sharaf

2010

Proceedings of 2010 IEEE International Symposium on Circuits and Systems

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“…Conventionally, a programmable divider is implemented using an extension of the dual-modulus divider in which the overall divide-by-2 sections are replaced with divide-by-2/3 blocks [2]. In the presented design, the programmability is achieved by the phase switching technique in which a multipelxer selects the appropriate phase of the D-Flip Flop.…”

Section: Architecturementioning

confidence: 99%

A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process

Zarei

Shoaei²,

Fakhraie³

et al.

ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445)

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A I .4 GHz programmable divider, whose modulus can be varied from 16 to 31 is presented with improved timing of multi-modulus divider structure and high-speed low-voltage embedded logic D-Flip Flop. Programmability is achieved by gating the feedback signal of the first latch of the divide-by-2 blocks. For high-speed operation, the first control stage, is implemented with a simple pseudo-NMOS logic gate. The programmable divider has been simulated in a 0.6pm digital CMOS technology with 13niW power consumption at 2.7V power supply and 1.4GHz maximum frequency.

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“…To eliminate this limit, the multi-modulus prescalerldivider is often used to provide more flexible divide ratios. One widely used scheme is cascading a number of ~2 1 3 stages [8], [9]. For example, nine stages are connected in cascade in [8], and any divide ratio between 5 12 and 1024 can be realized by external control signal.…”

mentioning

confidence: 99%

“…One widely used scheme is cascading a number of ~2 1 3 stages [8], [9]. For example, nine stages are connected in cascade in [8], and any divide ratio between 5 12 and 1024 can be realized by external control signal. Sometimes the multi-modulus prescalerldivider is designed to realize a certain range of divide ratio for a particular application [lo]- [12].…”

mentioning

confidence: 99%

Enhanced Phase Switching Prescaler

CMOS PLL Synthesizers: Analysis and Design

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This chapter is dedicated to the prescaler design. Conversional prescaler design techniques are overviewed, followed by the enhanced high-speed, low-power and robust phase-switching prescaler. The analysis and design of this new prescaler are elaborated in great detail. Prescaler architectureThe prescaler is included in the loop of the frequency synthesizer as shown in Fig. 3-1. It is in fact a high-speed frequency divider. For example, in a 2.4-GHz PLL in 0.35pm CMOS, the LC-VCO oscillates at 2.4GHz, but the frequency divider implemented with standard digital cells can only work at a frequency less than 400MHz. To bridge this speed gap, a specially designed high-speed frequency divider is needed. The prescaler is usually dual-modulus or multi-modulus in a tunable PLL. Conventional prescalerThe conventional dual-modulus prescaler [I]-[7] uses a dual-modulus synchronous counter as its input stage. Figure 5-1 shows the divide-by-415, divide-by-314 and divide-by-213 synchronous counters for the conventional prescaler. The flip-flops in these counters are usually specially designed high-speed ones.

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High-speed multi-modulus prescaler IC

Cited by 10 publications

References 2 publications

Extended division range 2/3 chain frequency divider with dynamic control word

Extended division range 2/3 chain frequency divider with dynamic control word

A 1.4 GHz/2.7 V programmable frequency divider for DRRS standard in 0.6 μm CMOS process

Enhanced Phase Switching Prescaler

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