High speed low power Full Adder circuit design using current comparison based domino

Ajayan, J.; Nirmal, D.; Sivasankari, S.; Sivaranjani, D.; Manikandan, M.

doi:10.1109/icdcsyst.2014.6926166

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Adder Using Hsd (High Speed Domino) Technique1

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Cited by 4 publications

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“…In adders based on HSD technique [2], P-Type keeper transistor (kt) pullup network reduce the current leakage which is connected to the kt. a clock signal is applied to its gate.…”

Section: Adder Using Hsd (High Speed Domino) Techniquementioning

confidence: 99%

High Performance Energy Efficient Computation Elements of Processing Unit

Rengasamy,

2019

IJEAT

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in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

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“…In adders based on HSD technique [2], P-Type keeper transistor (kt) pullup network reduce the current leakage which is connected to the kt. a clock signal is applied to its gate.…”

Section: Adder Using Hsd (High Speed Domino) Techniquementioning

confidence: 99%