High-Speed Logic Simulation on Vector Processors

Ishiura, Nagisa; Yasuura, Hiroto; Yajima, Shuzo

doi:10.1109/tcad.1987.1270276

Cited by 32 publications

(11 citation statements)

References 15 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In the present implementation the master task does not take part in the evaluation of the gates. 3 Mapping T-Algorithm: A Conventional Approach…”

Section: Master-slave Tasking Abstract I O Nmentioning

confidence: 99%

Distributed Digital Logic Simulation on a Network of Workstations

Sundaram¹

1994

1994 International Conference on Parallel Processing Vol. 3

View full text Add to dashboard Cite

A b s t r a c tGeneral purpose parallel processing machines are increasingly being used to speedup a variety of VLSI CA D applications.This paper addresses the mapping of logic simulation using the time first algorithm on parallel machines by exploting the concurrency available in the circuit being simulated.The speedup obtained on parallel/distributed simulation, depends on two major factors, the amount of simulation concurrency possible, and the amount of messages that must be passed among processors.Logic simulation using Time. First algorithm has been mapped to a distributed platform using a network of workstations.In this paper we propose a partitioning algorithm, which drastically reduces the interprocessor communication and also gives better simulation time. Reduction of communication data up to 4 t 0% with eight processors have been obtained for ISCAS benchmark circuits.Reduction of simulation time was also observed. K e y w o r d s : Logic S i m u l a t i o n , D i s t r i b u t e d P r o c e s s i n g , N e t w o r k of W o r k s t a t i o n s , T-A l g o r i t h m , F F R P a r t i t i o n i n g

show abstract

“…In the present implementation the master task does not take part in the evaluation of the gates. 3 Mapping T-Algorithm: A Conventional Approach…”

Section: Master-slave Tasking Abstract I O Nmentioning

confidence: 99%

Distributed Digital Logic Simulation on a Network of Workstations

Sundaram¹

1994

1994 International Conference on Parallel Processing Vol. 3

View full text Add to dashboard Cite

show abstract

“…Vector supercomputers offer another alternative to speeding up logic simulation. The event driven logic simulator by Ishiura et al [6] achieved a speedup of 8 by vectorization on the Hitachi S--810, although all operations were not vectorized. In this paper, we first present a parallel event-driven logic simulation algorithm in Section 2, which is designed for the shared memory model and is parallelized as well as being completely vectorized on the Cray Y-MP supercomputer.…”

Section: Introductionmentioning

confidence: 99%

“…The parallelization of the event-driven algorithm is based on concurrent evaluation, on different processors, of queued groups of events that reside in shared memory. Applying the approach used in [6] to the Cray Y-MP architecture, events are stored and processed in 64-event arrays to allow vectorization within a processor.…”

Section: Introductionmentioning

confidence: 99%

“…In Section 3, a parallel-and-vector fault simulation algorithm is presented where parallelization is achieved by performing independent gate evaluations concurrently on different processors. The data structure used in this research is similar to the data structure used in [6], for vector logic simulation. 1) Each entry of the State vector has the following information : the logic value of the gate output, the logic (8 inputs in our implementation), the number of fan-ins of the gate, and flags to be used by the simulator.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Parallel and Vector Logic and Fault Simulation Algorithms on the Cray Y-MP Supercomputer

Bataineh¹,

Özgüner

Szauter

1993

SIMULATION

View full text Add to dashboard Cite

In this paper, we present parallel algorithms for logic and fault simulation, developed for and implemented on the Cray Y-MP supercomputer, a general purpose sharedmemory parallel machine with vector processors. The parallel-and-vector version of the event-driven logic simulation algorithm achieves a speedup of 52 on the Cray Y-MP with 8 processors, with a maximum performance of about 2 million events per second. These results are comparable to the performance of hardware simulation engines and can be implemented on other parallel machines without major modifications. The second algorithm is a parallel and vector version of the parallel fault simulation algorithm. Experimental results on benchmark circuits [1] show that very high evaluation rates (20 to 32×10 9 evaluations/s.) can be achieved. Speedup factors of 45 to 69 are observed between the scalar and the parallel and vector execution of the fault simulator.

show abstract

“…The following encoding [7,8] of the 3 states allows for maximum simulation performance for standard AND, NAND, OR, NOR, and INVERTER gates:…”

Section: Ppsfp 3-value Simulationmentioning

confidence: 99%