High-speed/high-band width design methodologies for on chip DRAM core multimedia system LSIs

Abstract

Recently, as multimedia LSIs have developed, the demand for high-speed /high-band width LSIs which integrate the DRAM core and logic elements (CPU etc.) have been strongly required. However, the high-speed / high-band width operation induces the large switching noise. This noise degrades a DRAMS operating margin, and especially the data retention characteristics. In this paper, we analyze the noise transmission model and propose DRAM and logic compatible design methodology maintained the reliability of high-speed /highband width system LSIs. And we obtained good experimental results on the test device. 1.IntroductionIn the DRAM core implemented on system LSIs , there are three main problems as follows:(1) High speed switching in logic sections heats up the die and increases the junction leakage current, degrading the static refresh characteristics of DRAM. This heat problem has been solved by cooling systems and package technology.(2) The noise induced by large size buffer switching, in particular output buffers connected to large load capacitances degrades the dynamic refresh characteristics of the DRAM drastically. The dynamic refresh characteristics depend on the subthreshold leakage current of the access transistor and correspond to word line and substrate noise.(3) As a DRAM requires a boosted potential, the logic section cannot use the optimum transistor for the high speed switching in order to maintain the reliability of the gate oxide film.Here, we focus on the latter two problems and (2) in particular. We examined noise reduction techniques from the view point of circuits and device structures, and propose the best design approach for high-speed /high-band width system LSIs with a DRAM core. W L -0: Junction Leakage BL 0: Subthreshold Leakage 0 0.1 Vth Gate -source voltage Vgs (V) Fig. 1 DRAM cell leakage mechanism 2. The noise analysis for DRAM core implemented on 2.1 Degradation mechanism of dynamic refresh system LSIIn the logic section, a noise which level is lower than the CMOS threshold level is not a severe problem. However, in a DRAM core, noise on the word line increases the subthreshold leakage current of access transistors, exponentially. Fig. 1 shows the leakage mechanism of DRAM cell. If 0.1 V of noise appears on the word line, the leakage current increases ten times and the dynamic refresh time degrades, drastically. Fig. 2 shows the noise level on DRAM array GND level depends on the distance (Dis) between a DRAM core and a switching 20 ns/div. Fig.2 The waveforms of the noise level on DRAM array GND when the buffer is switching. Arrays (a) [Dis=100um] and (b) [Dis=7100uml are shown in Fig.11. 0-7803-3177-6 $5.00 0 1996 IEEE 13.2.1 265 IEEE 1996 CUSTOM INTEGRATED CIRCUITS CONFERENCE