High-speed hardware implementations of the KASUMI block cipher

Kitsos, Paris; Galanis, Michalis D.; Koufopavlou, O.

doi:10.1109/iscas.2004.1329330

Cited by 18 publications

(13 citation statements)

References 2 publications

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“…Table 2 shows that the pipelined architecture described in this document has the best performance among all of the designs proposed and reaches the highest clock frequency owing to its short critical path. Not only does it have a higher throughput than the design in [3], but is 2.4 times less expensive. The iterative architecture achieves higher throughput than the rest of the examined iterative proposals, this time due to its high clock frequency and its low latency.…”

Section: Synthesis Resultsmentioning

confidence: 99%

High performance encryption cores for 3G networks

Balderas-Contreras

Cumpliclo

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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This paper presents two novel and high performance hardware architectures, implemented in FPGA technology, for the KASUMI block cipher; this algorithm lies at the core of the confidentiality and integrity algorithms defined for the Universal Mobile Telecommunication System (UMTS) standard. The first proposal is a pipelined design and the second implements an iterative approach. The throughput for these architectures turn out to be higher than the throughput achieved by other proposals.

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Section: Synthesis Resultsmentioning

confidence: 99%

High performance encryption cores for 3G networks

Balderas-Contreras

Cumpliclo

2005

Proceedings of the 42nd Annual Conference on Design Automation - DAC '05

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“…The Type 2 architecture contains a four-stage inner-round pipelined FO module that results in an increased operating frequency and an improved throughput, by a factor of four. The two-round architecture described in [10] takes advantage of both inner-and outer-round pipeline techniques to decrease the period of the clock and increase the throughput. Inner-round registers are negative edge-triggered, whereas outerround registers are positive edge-triggered; consequently, the execution time of each round is one clock cycle.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…The S-boxes in this architecture are implemented with combinational logic. The two architectures reported in [11] are similar to that described in [10]. The authors look to reduce the area required by implementing a two-round iterative architecture.…”

Section: Performance Evaluationmentioning

confidence: 99%

“…As seen from the table, the number of hardware resources required by the extension is similar to those required by the architectures that implement the KASUMI algorithm using a reuse or hybrid approach. Note that, apart from the pipelined architecture described in [10], the proposed extension achieves the highest throughput/area ratio due to the efficient reutilization of the optimized two-round ciphering datapath.…”

Section: Performance Evaluationmentioning

confidence: 99%

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On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm

Balderas-Contreras

Cumplido

Feregrino-Uribe

2008

Computers & Electrical Engineering

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Modern cellular networks allow users to transmit information at high data rates, have access to IP-based networks deployed around the world, and access to sophisticated services. In this context, not only is it necessary to develop new radio interface technologies and improve existing core networks to reach success, but guaranteeing confidentiality and integrity during transmission is a must. The KASUMI block cipher lies at the core of both the f8 data confidentiality algorithm and the f9 data integrity algorithm for Universal Mobile Telecommunications System networks. KASUMI implementations must reach high performance and have low power consumption in order to be adequate for network components. This paper describes a specialized processor core designed to efficiently perform the KASUMI algorithm. Experimental results show two orders of magnitude performance improvement over software only based implementations. We describe the used design technique that can also be applied to implement other Feistel-like ciphering algorithms. The proposed architecture was implemented on a FPGA, results are presented and discussed.

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“…The architectures of MISTY1 and KASUMI can be categorised into high-speed and compact design implementations. For reconfigurable hardware design, a variety of area-efficient hardware architectures have been studied and found that compact design of both algorithms can be achieved with one round architectures [3][4][5][6][7][8]. The designs implementing RAM-based logic for substitution functions attain higher throughput utilising larger area [3].…”

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confidence: 99%

Highly optimised reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI

Yasir

Zhang

et al. 2017

Electron. lett.

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Highly optimised reconfigurable hardware architecture is proposed of 64 bit block ciphers MISTY1 and KASUMI for wide-area cryptographic applications. The reconfigurable hardware architecture is comprised of reconfigurable components consisting of FL function, FO/FI function and XOR function designed to perform MISTY1 and KASUMI algorithms round transformation functions. In addition, reconfigurable FO/FI function is adequate to generate MISTY1 extended keys for onward use in MISTY1 round transformation function. The substitution functions S9 and S7 for MISTY1 and KASUMI algorithms are optimised for area and throughput. Common subexpression elimination for AND-XOR logic combined with permutation/combination technique for AND gates reduces the area considerably, whereas parallel execution improves the throughput. With this design approach, application specific integrated circuit (ASIC) implementations using Synopsys Design Complier, SMIC 0.18 µm at 1.8 V achieved an area of 3481 NAND gates having throughput of 130.2 and 154.56 Mbits/s for MISTY1 and KASUMI, respectively. Synthesised FPGA implementation using Xilinx Artix 7 FPGA yielded an area of 487 configurable logic block (CLB) Slices having throughput of 209.43 and 248.7 Mbits/s for MISTY1 and KASUMI, respectively. Detailed design and performance analysis of reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI for ASIC implementations is described.

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High-speed hardware implementations of the KASUMI block cipher

Cited by 18 publications

References 2 publications

High performance encryption cores for 3G networks

High performance encryption cores for 3G networks

On the design and implementation of a RISC processor extension for the KASUMI encryption algorithm

Highly optimised reconfigurable hardware architecture of 64 bit block ciphers MISTY1 and KASUMI

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