2018
DOI: 10.1186/s13638-018-1117-2
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High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

Abstract: Multivariate signature belongs to Multivariate-Quadratic-Equations Public Key Cryptography (MPKC), which is secure to quantum computer attacks. Compared with RSA and ECC, it is required to speed up multivariate signature implementations. A high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this paper. The main computations of signature generations of multivariate schemes are additions, multiplications, inversions, and solving systems of linear equations (LSEs) in… Show more

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Cited by 4 publications
(1 citation statement)
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“…In order to determine the frequency of our pipelined implementation, time restrictions were imposed to the synthesis tool that determined a minimum clock period of 15.0 ns and, therefore, a clock frequency of 67 MHz. In Table Throughput (Mb/s) ECC-163 [23] UOV(30,10) [13] enTTS(28,20) [13] amTTS(34,24) [13] Rainbow(42,24) [25] DME-(3,2,48)…”
mentioning
confidence: 99%
“…In order to determine the frequency of our pipelined implementation, time restrictions were imposed to the synthesis tool that determined a minimum clock period of 15.0 ns and, therefore, a clock frequency of 67 MHz. In Table Throughput (Mb/s) ECC-163 [23] UOV(30,10) [13] enTTS(28,20) [13] amTTS(34,24) [13] Rainbow(42,24) [25] DME-(3,2,48)…”
mentioning
confidence: 99%