High-speed hardware architecture for implementations of multivariate signature generations on FPGAs

Abstract

Multivariate signature belongs to Multivariate-Quadratic-Equations Public Key Cryptography (MPKC), which is secure to quantum computer attacks. Compared with RSA and ECC, it is required to speed up multivariate signature implementations. A high-speed hardware architecture for signature generations of a multivariate scheme is proposed in this paper. The main computations of signature generations of multivariate schemes are additions, multiplications, inversions, and solving systems of linear equations (LSEs) in a finite field. Thus, we improve the finite field multiplications via using composite field expression and design a finite field inversion via using binary trees. Besides, we improve solving LSEs in a finite field based on a variant algorithm of Gauss-Jordan elimination and use the XOR gates to compute additions. We implement the high-speed hardware architecture based on the above improvements on an Altera Stratix Field-Programmable Gate Array (FPGA), which shows that it takes only 90 clock cycles and 0.9 μs to generate a multivariate signature. The comparison shows that the hardware architecture is much faster than other implementations.

High-throughput architecture for post-quantum DME cryptosystem

“…In order to determine the frequency of our pipelined implementation, time restrictions were imposed to the synthesis tool that determined a minimum clock period of 15.0 ns and, therefore, a clock frequency of 67 MHz. In Table Throughput (Mb/s) ECC-163 [23] UOV(30,10) [13] enTTS(28,20) [13] amTTS(34,24) [13] Rainbow(42,24) [25] DME-(3,2,48)…”