High speed energy efficient ALU design using Vedic multiplication techniques

MAC Implementation using Vedic Multiplication Algorithm

“…It produces 32 bit output. It is observed that for 16x16,and 32x32 proposed MAC module, the gate delay are 6.884ns,and 7.556ns while it is 22.604 ns, and 35.76 ns for the corresponding optimized Vedic multiplier described in [1].The total number of additions required in different bit size MAC are less compared to corresponding optimized Vedic multiplier due to the carry save adder used in MAC architecture. So MAC module uses less number of slices compared to optimized Vedic multiplier.…”

“…The MAC is implemented on a FPGA device XC2S200-6PQ208 using Xilinx ISE10.1 tool. The proposed design shows improvement of speed over the design presented in [1]. …”

“…So MAC module uses less number of slices compared to optimized Vedic multiplier. Hence, the proposed MAC module implementation found to be most efficient in terms of speed as compared to the scheme presented in [1]. .…”

“…A high speed energy efficient ALU design using Vedic mathematics is discussed in [1]. They have implemented ALU using adder, subtractor, Vedic multiplier, and MAC unit.…”

An Exhaustive Research Survey on Vedic ALU Design

“…In paper [40], M. Ramalatha, et.al, proposed a part of ALU design using Vedic multipliers. The authors used Vedic mathematics in designing multipliers and the proposed design is used to design MAC unit.…”