High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing

Bhandari, Sheetal U.; Subbaraman, Shaila; Pujari, Shashank; Cancare, Fabio; Bruschi, Francesco; Santambrogio, Marco D.; Grassi, Paolo Roberto

doi:10.1109/dsd.2012.74

Cited by 16 publications

(10 citation statements)

References 8 publications

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“…This unusual long time is due to the limitation of the partial reconfiguration in recent Altera FPGA. Actually, Altera FPGAs of the series V offers only an 1-Dimension column partial reconfiguration like the first Virtex-II Xilinx FPGAs [14]. However, two frames time is acceptable for sensor switch in non constrained applications.…”

Section: Evaluation and Resultsmentioning

confidence: 99%

Self-Adaptive Architecture for Multi-Sensor Embedded Vision System

Isavudeen

Dokladalova

Ngan

et al. 2016

Mathematical and Engineering Methods in Computer Science

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Architectural optimization for heterogeneous multi-sensor processing is a real technological challenge. Most of the vision systems involve only one single color sensor and they do not address the heterogeneous sensors challenge. However, more and more applications require other types of sensor in addition, such as infrared or low-light sensor, so that the vision system could face various luminosity conditions. These heterogeneous sensors could differ in the spectral band, the resolution or even the frame rate. Such sensor variety needs huge computing performance, but embedded systems have stringent area and power constraints. Reconfigurable architecture makes possible flexible computing while respecting the latter constraints. Many reconfigurable architectures for vision application have been proposed in the past. Yet, few of them propose a real dynamic adaptation capability to manage sensor heterogeneity. In this paper, a self-adaptive architecture is proposed to deal with heterogeneous sensors dynamically. This architecture supports on-the-fly sensor switch. Architecture of the system is self-adapted thanks to a system monitor and an adaptation controller. A stream header concept is used to convey sensor information to the self-adaptive architecture. The proposed architecture was implemented in Altera Cyclone V FPGA. In this implementation, adaptation of the architecture consists in Dynamic and Partial Reconfiguration of FPGA. The self-adaptive ability of the architecture has been proved with low resource overhead and an average global adaptation time of 75 ms.

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Section: Evaluation and Resultsmentioning

confidence: 99%

Self-Adaptive Architecture for Multi-Sensor Embedded Vision System

Isavudeen

Dokladalova

Ngan

et al. 2016

Mathematical and Engineering Methods in Computer Science

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“…ere are other existing PRCs proposed in the literature that are designed for standalone usage in hardware designs without any supporting processor [16][17][18][19]. Unfortunately their design files are not publicly available, with the exception of [20].…”

Section: Related Workmentioning

confidence: 99%

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

Kirchhoff

Kerling

Streitferdt

et al. 2019

International Journal of Reconfigurable Computing

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Modern FPGAs (Field Programmable Gate Arrays) are becoming increasingly important when it comes to embedded system development. Within these FPGAs, soft-core processors are often used to solve a wide range of different tasks. Soft-core processors are a cost-effective and time-efficient way to realize embedded systems. When using the full potential of FPGAs, it is possible to dynamically reconfigure parts of them during run time without the need to stop the device. This feature is called dynamic partial reconfiguration (DPR). If the DPR approach is to be applied in a real-time application-specific soft-core processor, an architecture must be created that ensures strict compliance with the real-time constraint at all times. In this paper, a novel method that addresses this problem is introduced, and its realization is described. In the first step, an application-specializable soft-core processor is presented that is capable of solving problems while adhering to hard real-time deadlines. This is achieved by the full design time analyzability of the soft-core processor. Its special architecture and other necessary features are discussed. Furthermore, a method for the optimized generation of partial bitstreams for the DPR as well as its practical implementation in a tool is presented. This tool is able to minimize given bitstreams with the help of a differential frame bitmap. Experiments that realize the DPR within the soft-core framework are presented, with respect to the need for hard real-time capability. Those experiments show a significant resource reduction of about 40% compared to a functionally equivalent non-DPR design.

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“…Partial reconfiguration has been widely used in diverse applications [5][6][7] that exploit the possibility to adapt hardware modules at run-time. A common requirement when using this technique is that the switching of hardware modules should be performed with minimal time overhead.…”

Section: Related Workmentioning

confidence: 99%

“…In contrast, [14,15] present controllers for Virtex-5 devices able to load partial bitstreams from BRAM and flash memory totally implemented in hardware and independent of the processor. In a similar way, [7,16] report implementations of processor-independent ICAP controllers for Virtex-4 FPGAs. Authors in [17] exploit DPR for the design of fault tolerant systems.…”

Section: Related Workmentioning

confidence: 99%

AC_ICAP: A Flexible High Speed ICAP Controller

Cardona

Ferrer

2015

International Journal of Reconfigurable Computing

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The Internal Configuration Access Port (ICAP) is the core component of any dynamic partial reconfigurable system implemented in Xilinx SRAM-based Field Programmable Gate Arrays (FPGAs). We developed a new high speed ICAP controller, named AC_ICAP, completely implemented in hardware. In addition to similar solutions to accelerate the management of partial bitstreams and frames, AC_ICAP also supports run-time reconfiguration of LUTs without requiring precomputed partial bitstreams. This last characteristic was possible by performing reverse engineering on the bitstream. Besides, we adapted this hardware-based solution to provide IP cores accessible from the MicroBlaze processor. To this end, the controller was extended and three versions were implemented to evaluate its performance when connected to Peripheral Local Bus (PLB), Fast Simplex Link (FSL), and AXI interfaces of the processor. In consequence, the controller can exploit the flexibility that the processor offers but taking advantage of the hardware speed-up. It was implemented in both Virtex-5 and Kintex7 FPGAs. Results of reconfiguration time showed that run-time reconfiguration of single LUTs in Virtex-5 devices was performed in less than 5 μs which implies a speed-up of more than 380x compared to the Xilinx XPS_HWICAP controller.

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High Speed Dynamic Partial Reconfiguration for Real Time Multimedia Signal Processing

Cited by 16 publications

References 8 publications

Self-Adaptive Architecture for Multi-Sensor Embedded Vision System

Self-Adaptive Architecture for Multi-Sensor Embedded Vision System

A Real-Time Capable Dynamic Partial Reconfiguration System for an Application-Specific Soft-Core Processor

AC_ICAP: A Flexible High Speed ICAP Controller

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