High speed digital filter design using register minimization retiming &amp;amp; parallel prefix adders

Yagain, Deepa; Krishna, A. Vijaya

doi:10.1109/eait.2012.6408014

Cited by 5 publications

(1 citation statement)

References 17 publications

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“…Since each delay element occupies about one-third of the binary adder, it is important to reduce the number of delay elements [11]. In retiming using register minimization, we can obtain the digital filter that uses minimum number of registers and satisfies the clock period constraints [15]. Here, forward splitting or register sharing [12] is used.…”

Section: (I) Calculatementioning

confidence: 99%

Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Yagain

Krishna

2014

VLSI Design

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Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

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Section: (I) Calculatementioning

confidence: 99%