Design of Synthesizable, Retimed Digital Filters Using FPGA Based Path Solvers with MCM Approach: Comparison and CAD Tool

Abstract

Retiming is a transformation which can be applied to digital filter blocks that can increase the clock frequency. This transformation requires computation of critical path and shortest path at various stages. In literature, this problem is addressed at multiple points. However, very little attention is given to path solver blocks in retiming transformation algorithm which takes up most of the computation time. In this paper, we address the problem of optimizing the speed of path solvers in retiming transformation by introducing high level synthesis of path solver algorithm architectures on FPGA and a computer aided design tool. Filters have their combination blocks as adders, multipliers, and delay elements. Avoiding costly multipliers is very much needed for filter hardware implementation. This can be achieved efficiently by using multiplierless MCM technique. In the present work, retiming which is a high level synthesis optimization method is combined with multiplierless filter implementations using MCM algorithm. It is seen that retiming multiplierless designs gives better performance in terms of operating frequency. This paper also compares various retiming techniques for multiplierless digital filter design with respect to VLSI performance metrics such as area, speed, and power.

Distributed Arithmetic RNS-based FIR Filter Design using Pipelining and Retiming Methods for High-Speed DSP Systems

“…In [8], the retiming method used with sequential circuits are covered by Jalaja et al From the viewpoint of complexity, Jiang and Brayton [9] synthesized the logic design. The multiplier-less multiple constant multiplication (MCM) technique has been retimed by Yagain and Vijaya [10]. Meher [11] has used cut-set and flexible retiming to enhance the CPD of traditional direct form filters at the expense of more sophisticated hardware.…”

High throughput FIR filter architectures using retiming and modified CSLA based adders

“…Jiang and Brayton [29] applied retiming to logic designs and synthesised the design from a complexity perspective. Yagain and Vijaya [30] have combined retiming with the multiplier‐less implementation of multiple constant multiplication algorithm. Meher [31] has applied cut‐set and flexible retiming to conventional direct form filters and achieved improvement in delay at the cost of increased hardware complexity.…”