High throughput FIR filter architectures using retiming and modified CSLA based adders

Abstract

A methodology to improve the throughput of FIR filters through the effective use of retiming and efficient add-multiply operation is presented in this study. Delay, energy and area efficient linear and square root carry-select adder (CSLA) structures are obtained by combining modified forms of carry look-ahead and carry-skip adder concepts to concatenated CSLA modules. The computational speed is enhanced by the quick generation and transmission of the end module carries by the module carry generation blocks. The delay performance of booth multiplier is improved by performing the partial product addition using the proposed square root CSLA. Two versions of the proposed filters are (a) high throughput low power and low complex retimed FIR filter and (b) high throughput energy efficient retimed FIR filter. The critical path delay, power, power-delay product and area-delay product of the proposed filter-2 are reduced by 71, 38, 82 and 78%, respectively, with respect to flexible retimed filter and by 40, 11, 47 and 37%, respectively, with respect to modified transpose form filter for a filter length of 64. Cadence software with gpdk 45 nm standard cell library is used for the design and implementation.

Area–delay and energy efficient multi‐operand binary tree adder

“…7 that the proposed BTA is best in terms of ADP and EDP than all the existing MOA designs. Compared to the recent MOA designs, the proposed BTA design for offers the saving in ADP and EDP by 22.5 and 28.7% than MOA of [30]; 54.5 and 62.7% than MOA of [31]; 44.1 and 48.2% than MOA of [32], respectively. It can also be seen from Fig.…”

“…The multi-operand BTA and WTA structures available in [5,6] respectively, are considered for comparison. The BTA structure of [5] Apart from this, the recent WTA design of [30] and MOA designs of [31,32] are also considered for comparison. All these designs and proposed BTA design are coded in VHDL for 8, 16 and 32 Similarly, the proposed 32-bit BTA involves 34.6% less area and 46.6% less energy than the MOA design of [31]; and 38.3% less area and 42.8% less energy than the MOA design of [32].…”

“…The BTA structure of [5] Apart from this, the recent WTA design of [30] and MOA designs of [31,32] are also considered for comparison. All these designs and proposed BTA design are coded in VHDL for 8, 16 and 32 Similarly, the proposed 32-bit BTA involves 34.6% less area and 46.6% less energy than the MOA design of [31]; and 38.3% less area and 42.8% less energy than the MOA design of [32]. It can also be observed from Table 4 that the delay performance of the proposed BTA is improving when the value of N is increasing, and it becomes comparable to the recent MOA designs for N = 32.…”

“…Similarly, the WTA structure of [6] is implemented in three different manners on the basis of recent fast adder used in the final sum stage of the design: (i) CLA [14]‐based WTA, (ii) PPA [21]‐based WTA and (iii) CSLA [25]‐based WTA. Apart from this, the recent WTA design of [30] and MOA designs of [31, 32] are also considered for comparison. All these designs and proposed BTA design are coded in VHDL for 8, 16 and 32 operands, each of 16 bits, and synthesised in Synopsys Design Compiler using TSMC 65 nm CMOS Library.…”

“…Subsequently, few CSKA designs are suggested to reduce the carry propagation delay [26][27][28]. Recently, few MOA structures are suggested in [29][30][31][32] for different applications. In [29,30], the MOA structure has been given for the accelerator design of the convolution neural network on field programmable gate array (FPGA), whereas the MOA designs of [31,32] have been suggested for motion estimation and FIR filter, respectively.…”