High Speed Bootstrapping Generic Voltage Level Shifter

Vaidya, Mahesh; Naugarhiya, Alok; Verma, Shrish

doi:10.1109/icaecc.2018.8479461

Cited by 2 publications

(1 citation statement)

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“…At the same time, the strength of the pull-down device is also increased using a lowpower auxiliary circuit. Bootstrapping generic voltage level shifter is proposed by Vaidya et al (2018). In 2014, Machiraju and Pushpamithra (2014) proposed the energy-efficient voltage level shifter (EVLS) circuits, which require only ten transistors and provide low power dissipation and low delay.…”

Section: Introductionmentioning

confidence: 99%

Performance analysis of multi-scaling voltage level shifter for low-power applications

Vaithiyanathan

Kurmi

Mishra

et al. 2020

WJE

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Purpose In complementary metal-oxide-semiconductor (CMOS) logic circuits, there is a direct square proportion of supply voltage on dynamic power. If the supply voltage is high, then more amount of energy will be consumed. Therefore, if a low voltage supply is used, then dynamic power will also be reduced. In a mixed signal circuit, there can be a situation when lower voltage circuitry has to drive large voltage circuitry. In such a case, P-type metal-oxide-semiconductor of high-voltage circuitry may not be switched off completely by applying a low voltage as input. Therefore, there is a need for level shifter where low-voltage and high-voltage circuits are connected. In this paper the multi-scaling voltage level shifter is presented which overcomes the contention problems and suitable for low-power applications. Design/methodology/approach The voltage level shifter circuit is essential for digital and analog circuits in the on-chip integrated circuits. The modified voltage level shifter and reported energy-efficient voltage level shifter have been optimally designed to be functional in all process voltage and temperature corners for VDDH = 5V, VDDL = 2V and the input frequency of 5 MHz. The modified voltage level shifter and reported shifter circuits are implemented using Cadence Virtuoso at 90 nm CMOS technology and the comparison is made based on speed and power consumed by the circuit. Findings The voltage level shifter circuit discussed in this paper removes the contention problem that is present in conventional voltage level shifter. Moreover, it has the capability for up and down conversion and reduced power and delay as compared to conventional voltage level shifter. The efficiency of the circuit is improved in two ways, first, the current of the pull-up device is reduced and second, the strength of the pull-down device is increased. Originality/value The modified level shifter is faster for switching low input voltage to high output voltage and also high input voltage to low output voltage. The average power consumption for the multi-scaling voltage level shifter is 259.445 µW. The power consumption is very less in this technique and it is best suitable for low-power applications.

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Section: Introductionmentioning

confidence: 99%