High-speed area-efficient inner-product processor

Tawfik, A.; El-Guibaly, F.; Fahmi, M.; Abdel-Raheem, Esam; Agathoklis, P.

doi:10.1109/cjece.1994.6591122

Cited by 9 publications

(10 citation statements)

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“…where s out , c out are the high-order sum and carry word output from the CS-MAC, respectively, l out is the low-order word output from the CS-MAC, s in , c in are the high-order sum and carry word input to the CS-MAC, respectively, and l in is the low-order word input to the CS-MAC. A reduction in the computation time ranging from 20 to 50% compared with other schemes has been achieved using the CS-MAC, without a significant increase in the required area [19]. Table 2 shows the activity for PE 0 (grey (light grey) circles) and PE 1 (blue (dark blue) circles) in Fig.…”

Section: Systolic Array Design Space Explorationmentioning

confidence: 96%

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Systolic array design space exploration of interpolators for multi‐rate systems

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents the development and comparison of interpolator systolic array designs and implementations. Systematic methodology was applied to the difference equations defining the interpolator algorithm. A dependence graph for the interpolator was obtained that combined the upsampler and the anti-imaging filter. Different data scheduling and projection operations were developed. Nine systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation. Field-programmable gate array implementations for the conventional and proposed designs confirm that the proposed interpolator implementation requires no more than 61.7% of the hardware resources required in the conventional design and are at least 63.9% faster than the conventional design.

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Section: Systolic Array Design Space Explorationmentioning

confidence: 96%

“…In the proposed design (Fig. 6b), a high-speed, double-precision carry-save multiplier/accumulator (CS-MAC) developed in [19] is used as…”

Section: Systolic Array Design Space Explorationmentioning

confidence: 99%

Systolic array design space exploration of interpolators for multi‐rate systems

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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“…6b, and later in Fig. 7b, a highspeed, double-precision carry-save MAC (CS-MAC) developed in [33] is used as…”

Section: Systolic Array Design Space Explorationmentioning

confidence: 99%

Decimator systolic arrays design space exploration for multirate signal processing applications

Shoukry

Gebali

Agathoklis

2019

IET Circuits, Devices & Systems

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This study presents a new systolic array structure for a decimator that merges the antialiasing finite impulse response (FIR) filter with the downsampler. The development of the structure is based on a systematic methodology. Using this methodology, a dependence graph for the decimator was obtained that combined the antialiasing filter and the downsampler. Different data scheduling and projection operations were developed to obtain different proposed designs. Six systolic array design options were obtained and evaluated. The fastest design was selected for hardware implementation and compared with the other two well known decimator designs; namely, conventional design, in which the antialiasing filter is followed by a downsampling and the polyphase design, in which a commutator is followed by the polyphase antialiasing filter. Fieldprogrammable gate array implementations for the proposed and the other two designs confirm that the proposed decimator implementation outperforms in terms of area, speed, and power as the decimation factor increases regardless of the number of FIR filter coefficients.

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“…The proposed scheme first makes pre-computations in parallel, and then merges all partial results for a faster solution. The implementation in [9] is an example of a 3-step solution. The principle is to perform concurrently addition with the saved carries and multiplication between the two new numbers, which is called "multiply-accumulate" .…”

Section: Choice Of Techniquementioning

confidence: 99%

“…The techniques to realize such designs are explained in [5, 6, 71. Examples given in [5, 71 explain the CSIPP(Carry-Save Inner Product Processor) used in [8] and described in [9].…”

Section: Available Techniquesmentioning

confidence: 99%