High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder

Hasan, Mehedi; Biswas, Parag; Alam, Md. Shihabul; Zaman, Hasan U.; Hossain, Mainul; Islam, Sharnali

doi:10.1109/icccnt45670.2019.8944524

Cited by 20 publications

(6 citation statements)

References 18 publications

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“…where, 0< i < 3 and "i" is integer number C=Carry terms G i =AB (Carry Generate Term) P i =A i B i (Carry Propagate Term) Based on the observations on the equations stated above, it can be clearly said that the carry generation circuit would require AND and XOR gate since the Boolean expression of the G i and the P i terms represents AND and XOR operations respectively. As per [33], CLA circuits for 4-bit CLA adder are represented in Figure 2. The circuits for designing G i and P i terms are depicted by Figure 3.…”

Section: Conventional 4-bit Cla Adder Design Methodologymentioning

confidence: 99%

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Hasan¹,

Islam²,

Ahmed³

2019

CSSP

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Carry Look-Ahead Adder (CLA) is considered as one of the most widely used adder topologies which are used in high performance computing systems. In this research, an improved version of 4-bit CLA adder has been proposed. Performance improvement of 4-bit CLA adder has been made by using hybrid AND and XOR gates in the input side for generating carry propagate and carry generate terms. The CLA circuits are kept exactly the same as the conventional one. Performance of the proposed modified 4-bit CLA adder has been evaluated and compared with the conventional design using Cadence tools in 90 nm technology node. Performance has been evaluated and compared in terms of average power, propagation delay and power delay product. The proposed modified design exhibited significant improvement in performance while compared with the conventional one. Enhancement done by the proposed 4-bit CLA adder design in average power, propagation delay and PDP were 14.96%, 11.76% and 25.32% respectively. In addition to performance enhancement, transistor count require for the proposed design is quite less compared to the conventional design which result in less surface area on chip. Moreover, less transistor count accounts for less power dissipation. Hence, utilizing the proposed design in modern high-performance computing systems would bring about high-performance improvements.

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Section: Conventional 4-bit Cla Adder Design Methodologymentioning

confidence: 99%

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Hasan¹,

Islam²,

Ahmed³

2019

CSSP

Self Cite

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“…In circuit design, it becomes necessary to have a comparison of the performance parameters [80][81][82][83]. Based on the performance comparison parameters of QCA FAs discussed above, a summary is provided in Table 1.…”

Section: Design and Performancementioning

confidence: 99%

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Joy

Chakraborty

Islam

et al. 2023

Advances in Materials Science and Engineering

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Being one of the promising techniques for future computing systems, quantum-dot cellular automata (QCA)-based circuit design has gained massive interest among researchers due to which numerous QCA-based full adder (FA) circuits have been designed. Due to numerous QCA FA circuits available in the existing literature, researchers find it difficult to invest the time to search, implement, simulate, and analyze QCA FAs to find the best-suited design according to their needs. Existing review articles do not present a complete overview and performance comparison of QCA FAs. Also, the existing articles do not include quite a number of QCA FA designs in the literature review. As a result, a detailed review including all possible QCA FAs becomes essential. Therefore, rather than going for a new QCA FA design, this research aims to aid researchers by providing an extensive literature review and comprehensive study on existing QCA FAs. A total of 47 QCA FAs have been considered for analysis. The QCA FA implementation method and performance parameters are summarized in a tabular manner to provide a quick overview and comparison of the QCA FAs.

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“…20 The G i represents AND operation of the input terms A i and B i (G i = A i B i ) . 21 On the other hand, P i represents XOR operation of the input terms A i and B i ( 20 Based on G i and P i terms, Boolean representation of carry terms are 21 :…”

Section: Static Cmos Logic Based Conventional 4-bit Clamentioning

confidence: 99%

“…The

{G}_{\mathrm{i}}

represents AND operation of the input terms

{A}_{\mathrm{i}}

and

{B}_{\mathrm{i}}\ \left({G}_i={A}_i\ {B}_i\right).

21 On the other hand,

{P}_{\mathrm{i}}

represents XOR operation of the input terms

{A}_{\mathrm{i}}

and

{B}_{\mathrm{i}}

(

{P}_i={A}_i\oplus {B}_i

) 20 . Based on

{G}_i

and

{P}_i

terms, Boolean representation of carry terms are 21 :

{C}_1={G}_0+{P}_0{C}_0

{C}_2={G}_1+{P}_1{G}_0+{P}_1{P}_0{C}_0

…”

Section: Literature Review Of Existing 4‐bit Clamentioning

confidence: 99%

“…$$ 21 On the other hand,

{P}_{\mathrm{i}}

represents XOR operation of the input terms

{A}_{\mathrm{i}}

and

{B}_{\mathrm{i}}

(

{P}_i={A}_i\oplus {B}_i

) 20 . Based on

{G}_i

and

{P}_i

terms, Boolean representation of carry terms are 21 :

{C}_1={G}_0+{P}_0{C}_0

{C}_2={G}_1+{P}_1{G}_0+{P}_1{P}_0{C}_0

{C}_3={G}_2+{P}_2{G}_1+{P}_2{P}_1{G}_0+{P}_2{P}_1{P}_0{C}_0

C_{4} goodbreak= G_{}

…”

Section: Literature Review Of Existing 4‐bit Clamentioning

confidence: 99%

See 1 more Smart Citation

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

Hasan

Chowdhury

Faruqe

et al. 2023

Engineering Reports

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This research aims to fill up the research gap in energy‐efficient transistor‐level wide word‐length carry circuit generator by using ripple carry (RC) and carry look‐ahead (CLA) method‐based hybrid 4‐bit carry generation process for wide word‐length carry‐select adder (CSLA). Compared to the existing 4‐bit CLA architectures, the proposed 4‐bit RC‐CLA method‐based hybrid 4‐bit carry generator showed performance improvement in terms of power and power delay product (PDP). Later, the 4‐bit carry architectures (existing and proposed) were used as a base to implement 16‐bit carry select adder (CSA) in order to investigate and compare the effect of using the proposed hybrid RC‐CLA based 4‐bit carry generator in large structures. Unlike 4‐bit operation, the proposed design displayed the best performance in power and PDP for 16‐bit CSA extension, which proves its effectiveness in wide word‐length adder structures.

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High Speed and Ultra Low Power Design of Carry-Out Bit of 4-Bit Carry Look-Ahead Adder

Cited by 20 publications

References 18 publications

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Performance Improvement of 4-Bit Static CMOS Carry Look-Ahead Adder Using Modified Circuits for Carry Propagate and Generate Terms

Quantum-Dot Cellular Automata-Based Full Adder Design: Comprehensive Review and Performance Comparison

Wide word‐length carry‐select adder design using ripple carry and carry look‐ahead method based hybrid 4‐bit carry generator

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