High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

Fukami, Shunsuke; Yamanouchi, Michihiko; Koyama, Tanetoshi; Ueda, Kunihiro; Yoshimura, Y.; Kim, K.-J.; Chiba, Daichi; Honjo, Haruo; Sakimura, N.; Nebashi, R.; Kato, Y.; Tsuji, Yoshiyuki; Morioka, A.; Kinoshita, Keizo; Miura, S.; Suzuki, T.; Tanigawa, H.; Ikeda, Shoji; Sugibayashi, Toshio; Kasai, N.; Takahisa, Ono; Ohno, Hideo

doi:10.1109/vlsit.2012.6242461

Cited by 25 publications

(14 citation statements)

References 1 publication

Supporting

Mentioning

Contrasting

Order By: Relevance

“…To tackle this issue, a field-free deterministic SOT switching was reported in the literature and enacted by utilizing a lateral wedge oxide, 7 tilted magnetic easy axis, 8 antiferromagnetic layer, 9,10 or hybrid ferromagnetic/ ferroelectric structure. 11 On the other hand, an alternative three-terminal magnetic memory was reported using the STT-driven domain wall (DW) motion, 12,13 where the switching is achieved by moving a DW back and forth along the magnetic wire. The key requirement of the DW motion device is to initialize the magnetization at the two ends of wire in opposite directions.…”

mentioning

confidence: 99%

Field-Free Spin–Orbit Torque Switching from Geometrical Domain-Wall Pinning

et al. 2018

View full text Add to dashboard Cite

Spin-orbit torques, which utilize spin currents arising from the spin-orbit coupling, offer a novel method for the electrical switching of the magnetization with perpendicular anisotropy. However, the necessity of an external magnetic field to achieve deterministic switching is an obstacle for realizing practical spin-orbit torque devices with all-electric operation. Here, we report field-free spin-orbit torque switching by exploiting the domain-wall motion in an anti-notched microwire with perpendicular anisotropy, which exhibits multidomain states stabilized by the domain-wall surface tension. The combination of spin-orbit torque, Dzyaloshinskii-Moriya interactions, and domain-wall surface-tension-induced geometrical pinning allows the deterministic control of the domain wall and offers a novel method to achieve a field-free spin-orbit torque switching. Our work demonstrates the proof of concept of a perpendicular memory cell that can be readily adopted in three-terminal magnetic memory.

show abstract

mentioning

confidence: 99%

Field-Free Spin–Orbit Torque Switching from Geometrical Domain-Wall Pinning

et al. 2018

View full text Add to dashboard Cite

show abstract

“…The DW integration determines the number of ones in a given bit stream. According to the experimental work reported in [44], the reliability of a typical domain wall device is excellent. For example, a Co/Ni wire can achieve a 10-year retention time at 150 degrees and 1 × 10 14 times write.…”

Section: Error Analysismentioning

confidence: 99%

“…For example, a Co/Ni wire can achieve a 10-year retention time at 150 degrees and 1 × 10 14 times write. In addition, the experiments in [44] have also shown that the domain wall velocity and critical current are not sensitive to external magnetic field or temperature.…”

Section: Error Analysismentioning

confidence: 99%

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

Bai

Lin

2016

JLPEA

View full text Add to dashboard Cite

This paper describes the stochastic-based Spin-Programmable Gate Array (SPGA), an innovative architecture attempting to exploit the stochastic switching behavior newly found in emerging spintronic devices for reconfigurable computing. While many recently studies have investigated using Spin Transfer Torque Memory (STTM) devices to replace configuration memory in field programmable gate arrays (FPGAs), our study, for the first time, attempts to use the quantum-induced stochastic property exhibited by spintronic devices directly for reconfiguration and logic computation. Specifically, the SPGA was designed from scratch for high performance, routability, and ease-of-use. It supports variable-granularity multiple-input-multiple-output (MIMO) logic blocks and variable-length bypassing interconnects with a symmetrical structure. Due to its unconventional architectural features, the SPGA requires several major modifications to be made in the standard VPR placement/routing CAD flow, which include a new technology mapping algorithm based on computing (k, l)-cut, a new placement algorithm, and a modified delay-based routing procedure.Previous studies have shown that, simply replacing reconfiguration memory bits with spintronic devices, the conventional 2D island-style FPGA architecture can achieve approximately 5 times area savings, 2 times speedup and 1.6 times power savings. Our mixed-mode simulation results have shown that, with FPGA architecture innovations, on average, a SPGA can further achieve more than 10 times improvement in logic density, about 5 times improvement in average net delay, and about 5 times improvement in the critical-path delay for the largest 12 MCNC benchmark circuits over an island-style baseline FPGA with spintronic configuration bits.

show abstract

“…Our delay circuit uses the design of an MRAM device with four terminals, such as a domain wall motion (DWM) device [5], and a spin-Hall-effect (SHE) device [6][7] [8] to overcome this issue. The four-terminal device is shown in Fig.…”

Section: A Designmentioning

confidence: 99%

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Nebashi

Sakimura

Honjo

et al. 2014

2014 IEEE International Symposium on Circuits and Systems (ISCAS)

View full text Add to dashboard Cite

A delay circuit using four-terminal magneticrandom-access-memory (MRAM) devices was designed for power-efficient time-domain signal processing. A cell area of 6.4 m 2 was obtained using 90-nm CMOS/MRAM technologies. The basic operations to both store the data and control the delay time were confirmed on the fabricated test chips. In addition, we proposed a power-efficient neuromorphic core using the delay circuit.

show abstract

High-speed and reliable domain wall motion device: Material design for embedded memory and logic application

Cited by 25 publications

References 1 publication

Field-Free Spin–Orbit Torque Switching from Geometrical Domain-Wall Pinning

Field-Free Spin–Orbit Torque Switching from Geometrical Domain-Wall Pinning

Stochastic-Based Spin-Programmable Gate Array with Emerging MTJ Device Technology

A delay circuit with 4-terminal magnetic-random-access-memory device for power-efficient time- domain signal processing

Contact Info

Product

Resources

About