High-speed and low-power split-radix FFT

Yeh, Wen-Chang; Jen, Chein-Wei

doi:10.1109/tsp.2002.806904

Cited by 129 publications

(2 citation statements)

References 17 publications

(32 reference statements)

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“…The paper reports the experimental results of the proposed architecture in 250 nm, 180 nm, 130 nm, and 90 nm standard CMOS library. Wen-Chang Yeh et al [13] in their paper presented a novel split-radix fast Fourier transform (SRFFT) pipeline architecture design using mapping methodology. The latency between complex multiplication and butterfly operation is balanced.…”

Section: Literature Surveymentioning

confidence: 99%

A New Clock Gated Flip Flop for Pipelining Architecture

Krishnamoorthy¹,

Saravanan²

2016

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The objective of the work is to design a new clock gated based flip flop for pipelining architecture. In computing and consumer products, the major dynamic power is consumed in the system's clock signal, typically about 30% to 70% of the total dynamic (switching) power consumption. Several techniques to reduce the dynamic power have been developed, of which clock gating is predominant. In this work, a new methodology is applied for gating the Flip flop by which the power will be reduced. The clock gating is employed to the pipelining stage flip flop which is active only during valid data are arrived. The methodology used in project named Selective Look-Ahead Clock Gating computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. Similarly to data-driven gating, it is capable of stopping the majority of redundant clock pulses. In this work, the circuit implementation of the various blocks of data driven clock gating is done and the results are observed. The proposed work is used for pipelining stage in microprocessor and DSP architectures. The proposed method is simulated using the quartus for cyclone 3 kit.

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Section: Literature Surveymentioning

confidence: 99%

A New Clock Gated Flip Flop for Pipelining Architecture

Krishnamoorthy¹,

Saravanan²

2016

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“…Fast Fourier transform (FFT) is one of the most fundamental algorithms used in digital signal processing area. Many applications such as orthogonal frequency division multiplexing (OFDM) [1,2,3,4,5,6], long term evolution (LTE) [7,8,9,10,11,12,13] and ultra-wideband (UWB) systems [14,15,16,17,18,19,20] require an area efficient, high accuracy FFT processor. Traditional FFT architectures include: memory-based, pipelined, and array architectures.…”

Section: Introductionmentioning

confidence: 99%

Implementation of a radix-2<sup>k</sup> fixed-point pipeline FFT processor with optimized word length scheme

Pang

Dong

Jin

et al. 2019

IEICE Electron. Express

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To design a high-precision and low-complexity FFT/IFFT processor architecture, the optimum bit sizing technique in each stage is usually adopted. However, it is difficult to provide an accurate, fast word length scheme due to the diversity of FFT algorithms and the complexity of circuit structure. In this paper, we focus on the widely-used radix-2 k Decimation-In-Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Based on our previous research on fixed-point FFT Signal-to-Quantization-Noise Ratio (SQNR) assessment, an analytical expression of word lengths in different stages is deduced. We further put forward a word length optimization method based on the analytical expression. Pre-layout logic synthesis and power simulation are performed for comparison with some previous works. Eventually, we implement a 16384-point FFT processor in 0.13 µm technology. The proposed method yields more hardware resource benefit and saves more simulation time.

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Accelerations of Zhao's methods for the numerical inversion of Laplace transform

Chen

Mei

2011

Int. J. Numer. Meth. Biomed. Engng.

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SUMMARYZhao recently presented two accurate and universal approaches to the numerical inversion of the Laplace transform. Both approaches are based on irregularly spaced intervals. Compared with the conventional approach by Durbin, the computational burden of Zhao's approaches is significantly heavier. In this report, the author proposed refinements by which the efficiency of Zhao's approaches can be improved significantly. This is achieved by subdividing the entire integrating range into several sub-bands, but the sampling interval in each sub-band is constant. In this way, the computation is accelerated by either applying Clenshaw's recurrence or the Chirp-Z transform. The efficiency of both accelerating approaches is verified numerically by three examples, which makes Zhao's two approaches practicable. In addition, the history of applying the fast Fourier transform to the Laplace transform is reviewed briefly.

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High-speed and low-power split-radix FFT

Cited by 129 publications

References 17 publications

A New Clock Gated Flip Flop for Pipelining Architecture

A New Clock Gated Flip Flop for Pipelining Architecture

Implementation of a radix-2<sup>k</sup> fixed-point pipeline FFT processor with optimized word length scheme

Accelerations of Zhao's methods for the numerical inversion of Laplace transform

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