Implementation of a radix-2^k fixed-point pipeline FFT processor with optimized word length scheme

Abstract

To design a high-precision and low-complexity FFT/IFFT processor architecture, the optimum bit sizing technique in each stage is usually adopted. However, it is difficult to provide an accurate, fast word length scheme due to the diversity of FFT algorithms and the complexity of circuit structure. In this paper, we focus on the widely-used radix-2 k Decimation-In-Frequency (DIF) Fast Fourier Transform (FFT) algorithm. Based on our previous research on fixed-point FFT Signal-to-Quantization-Noise Ratio (SQNR) assessment, an analytical expression of word lengths in different stages is deduced. We further put forward a word length optimization method based on the analytical expression. Pre-layout logic synthesis and power simulation are performed for comparison with some previous works. Eventually, we implement a 16384-point FFT processor in 0.13 µm technology. The proposed method yields more hardware resource benefit and saves more simulation time.