High-speed and low-power FeRAM utilising merged BL/PL array architecture with twin-bitline-driven scheme

Zhang, G.; Jia, Zhou; Ren, Tian‐Ling; Chen, H.

doi:10.1049/el.2009.0173

Cited by 4 publications

(2 citation statements)

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“…It equals Cox WLl2 when the MOS transistor works in the linear region and it equals 2Cox WLl3 while it works in the saturation region. Thus the gate-source capacitance Cb-w (2) can be easily calculated. The bulk junction capacitance Cb-gnd can be described as: (3) in which, Cj and Cjsw stand for the junction capacitance per unit junction bottom wall area at zero-bias and junction capacitance per unit junction periphery at zero-bias.…”

Section: Resultsmentioning

confidence: 99%

High-speed and low-power FRAM with a bitline-segmental array

Jia

Liu

Tao

et al. 2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 J.1 m 3-metal process and functionally verified.

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Section: Resultsmentioning

confidence: 99%

High-speed and low-power FRAM with a bitline-segmental array

Jia

Liu

Tao

et al. 2014

2014 IEEE International Conference on Electron Devices and Solid-State Circuits

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“…Introduction: Ferroelectric random access memory (FRAM) is a promising non-volatile memory, among which 1T1C (one transistor and one capacitor)-type FRAM has more competitiveness for embedded and standalone data storage applications with technologies of integrated circuits scaled down [1][2][3][4]. To generate a reference signal for data-sensing is a challenge for the 1T1C-type FRAM design [5,6].…”

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confidence: 99%

Reference voltage generation scheme enhancing speed and reliability for 1T1C‐type FRAM

et al. 2014

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An improved reference voltage generation scheme is proposed for a 1T1C-type ferroelectric random access memory (FRAM), in which the circuit referring to reference cells is redefined and the data are written into reference cells at random between '1' and '0' depending on the voltages of the bitlines during every operation cycle. Compared with conventional schemes, it can not only realise higher access speed for memory, but also can enhance its reliability by resolving the imprint and relieving the fatigue relating to ferroelectric capacitors in the device. Functional verification for the experimental prototype utilising the proposed scheme has been implemented.

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