2013
DOI: 10.1109/led.2012.2233708
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High-Robustness and Low-Capacitance Silicon-Controlled Rectifier for High-Speed I/O ESD Protection

Abstract: A high-robustness and low-capacitance clamp for on-chip electrostatic discharge (ESD) protection is developed. The low capacitance is obtained by mitigating the capacitance associated with the lightly doped n-well/p-well junction. In addition to minimizing the capacitance, the high ESD robustness is achieved by optimizing independently within the same structure a silicon-controlled rectifier and a diode for the forward and reverse conduction processes, respectively. The new clamp with an area of 50 × 10 μm 2 i… Show more

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Cited by 41 publications
(15 citation statements)
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“…Table 2 summarizes the electrical properties according to changes in design variables. are important because they affect the electrical characteristics and It2 of the circuit [15]. Carrier mobility at high temperatures increases the resistance value of the N well and well regions and results in a lower holding current.…”
Section: Tablementioning
confidence: 99%
“…Table 2 summarizes the electrical properties according to changes in design variables. are important because they affect the electrical characteristics and It2 of the circuit [15]. Carrier mobility at high temperatures increases the resistance value of the N well and well regions and results in a lower holding current.…”
Section: Tablementioning
confidence: 99%
“…Thermal reliability is very important because it affects the latch-up immunity and electrical properties of the device. In the thermal reliability experiment, the hot chuck controller heats the wafer and the TLP system is used to monitor changes in the electrical properties [19]. Carrier mobility at high temperatures reduces the holding current by increasing the resistance of the well and substrate.…”
Section: Introductionmentioning
confidence: 99%
“…Of course, low turn-on voltage, reasonable holding voltage and low leakage current are required. A low capacitance, about 94fF at zero bias, is obtained in [5]. However, the triggering voltage (V t1 ) of 8.1V is still high for many low voltage RFICs.…”
Section: Introductionmentioning
confidence: 99%
“…In addition, a complete full-chip ESD protection scheme often requires multiple ESD protection structures for each pin to protect against ESD surges of different modes, i.e., positive and negative ESD pulses from I/O to VSS (PS & NS modes), positive and negative ESD transients from I/O to VDD (PD & ND models), as well as ESD surge from VDD to VSS (DS model). So there should require multiple ESD protection cell reported in [5], and this will significantly increase parasitic parameter and consumption of silicon area, which are intolerable to advanced RFICs.…”
Section: Introductionmentioning
confidence: 99%