High-quality Ge epilayers on Si with low threading-dislocation densities

Luan, Hsin-Chiao; Lim, Desmond R.; Lee, Kevin K.; Chen, Kevin; Sandland, Jessica G.; Wada, Kazumi; Kimerling, Lionel C.

doi:10.1063/1.125187

Cited by 672 publications

(385 citation statements)

References 12 publications

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“…4(b). The density tends to be reduced with increasing the layer thickness [19], while a post-growth annealing at high temperatures (800-900°C) [18] is effective to reduce the threading dislocation density below 10 8 cm −2 , as in the bottom of Fig. 4(b) and in Fig.…”

Section: Epitaxial Growth Of Ge On Simentioning

confidence: 86%

“…A large surface roughness should be also induced as the result of three-dimensional Stranski-Krastanov growth. Luan et al [18] reported that a uniform epitaxial layer of Ge is directly grown on Si (001) wafer by ultrahighvacuum chemical vapor deposition (UHV-CVD) with a low-high temperature (typically 350°C/600°C) two-step growth. Fig.…”

Section: Epitaxial Growth Of Ge On Simentioning

confidence: 99%

“…4(c). Ge can be grown on selective areas of Si surface with SiO 2 masks [18,20,21]. Typical optical and scanning electron microscope images taken by the authors are shown in Figs.…”

Section: Epitaxial Growth Of Ge On Simentioning

confidence: 99%

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Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ishikawa

Saito

2014

IEICE Electron. Express

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Section: Epitaxial Growth Of Ge On Simentioning

confidence: 86%

Section: Epitaxial Growth Of Ge On Simentioning

confidence: 99%

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Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ishikawa

Saito

2014

IEICE Electron. Express

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“…compressive-strain-induced defects will normally increase the dark current of p-i-n photodiodes. A two-step germanium growth technique with subsequent annealing is now widely used to prevent 'islanding' during ultrahigh-vacuum chemical vapor deposition and to reduce defect generation [36]. By releasing the compressive strain arising from lattice mismatch through the introduction of a low-temperature buff er layer, the tensile strain caused by the diff erence in thermal expansion coeffi cients was shown to improve the performance of germanium-on-silicon diode photodetectors [37].…”

Section: Integrated Silicon Photodetectorsmentioning

confidence: 99%

Device engineering for silicon photonics

Chen

Tsang

2011

NPG Asia Mater

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A fter an impressive initial spurt of progress in device engineering during the early 2000s when the optical communications industry saw unprecedented levels of investment, silicon photonics continues to develop at an amazing pace. Many novel applications and devices are emerging. Silicon photonics has the potential to become a major platform for optoelectronic integrated circuits (OEICs) and to be used in high-speed optical interconnects for chip-level data communications because of the extremely large bandwidth and high speed off ered by optical communications. Many challenges have been addressed through the introduction of innovative ideas, paving the way for the practical deployment of silicon-based optoelectronic devices and integrated photonic circuits in computing and telecommunication systems [1]. Th e commercialization of silicon photonics, originally driven by applications in telecommunications, is now also driven by the needs of the computing industry for highspeed, energy-effi cient optical cable technology, such as the Light Peak Technology under development by Intel (USA). Th e California-based company Luxtera (USA) has also commercialized a series of siliconphotonic transceiver systems.Silicon off ers many advantages over alternative material systems (e.g. InP, GaAs, LiNbO 3 ) for OEIC applications. One major reason for the wide interest that silicon photonics is attracting is the cost advantage that silicon photonics can potentially off er through its compatibility with the complementary metal-oxide-semiconductor (CMOS) fabrication processes used in the microelectronics industry. Th e huge investments that have been made in CMOS microelectronics fabrication technologies has resulted in processes that off er much higher yield than is possible using alternative materials for photonics, thus making feasible large-scale integration and the production of silicon-photonic devices that are monolithically integrated with not only optical components but also electronic circuits in the same platform at ultrahigh density. Another reason for the attractiveness of silicon photonics is the high refractive index contrast between the silicon core (refractive index, 3.48) and silicon dioxide cladding (refractive index, 1.45) in silicon-on-insulator (SOI) devices, which ensures the submicrometer confi nement of light and allows tight bending in optical waveguides. Th e high-density integration of photonic circuits on SOI platforms is thus feasible. Th e low cost of high-quality SOI wafers is another advantage of silicon photonics. All kinds of low-cost devices enabled by silicon photonics are therefore predicted, and these may also enjoy the other benefi ts of monolithic integration: smaller size, increased power effi ciency and improved reliability. Figure 1 shows an example of a high-density integrated photonics devices fabricated on a 6-inch SOI wafer using CMOS-compatible technology.In this article, we review some of the exciting progress that has been made in silicon photonics with the aim of providing a broa...

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“…It has been shown that TDs in Ge are of 60°glissile type, and the reduction in their density on annealing has been postulated to take place by thermal stress-induced glide and annihilation. 14 The residual strain of all the films listed in Table I was characterized using HRXRD. Figure 5 shows the lattice parameter versus sin 2 w plot for sample A (annealed 0.7 lm Ge) with data points fitted to a bestfit linear regression line along with the R 2 value, a measure of the quality of fit.…”

mentioning

confidence: 99%

Poisson Ratio of Epitaxial Germanium Films Grown on Silicon

Bharathan

Narayan

Rozgonyi

et al. 2012

Journal of Elec Materi

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An accurate knowledge of elastic constants of thin films is important in understanding the effect of strain on material properties. We have used residual thermal strain to measure the Poisson ratio of Ge films grown on Si h001i substrates, using the sin 2 w method and high-resolution x-ray diffraction. The Poisson ratio of the Ge films was measured to be 0.25, compared with the bulk value of 0.27. Our study indicates that use of Poisson ratio instead of bulk compliance values yields a more accurate description of the state of in-plane strain present in the film.

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High-quality Ge epilayers on Si with low threading-dislocation densities

Cited by 672 publications

References 12 publications

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Ge-on-Si photonic devices for photonic-electronic integration on a Si platform

Device engineering for silicon photonics

Poisson Ratio of Epitaxial Germanium Films Grown on Silicon

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