High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

Chen, Poki; Lan, Jian-Ting; Wang, Ruei-Ting; Qui, Nguyen My; Marquez, John Carl Joel S.; Kajihara, Seiji; Miyake, Y.

doi:10.1109/tvlsi.2019.2962606

Cited by 17 publications

(13 citation statements)

References 32 publications

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“…There is a growing research trend for high-resolution TDCs due to increasing demands for high-precision PET imaging, early medical diagnosis, or biosensing [21], [29], [30]. Many architectures and methods, including the dual-sampling structure, the Vernier delay line, the multi-phase design, the multi-chain design and the wave-union method, were proposed to overcome process-related limitations improve TDC resolutions [31]- [35]. Other logic resources, for example, routings and digital signal processing (DSP) blocks, can also be used to build TDCs [36], [37].…”

Section: Introductionmentioning

confidence: 99%

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128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Xie

Wang

Chen

et al. 2022

IEEE Trans. Ind. Electron.

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This paper proposes a new calibration method, called the mixed-binning (MB) method, to pursue highlinearity time-to-digital converters (TDCs) for light detection and ranging (LiDAR) applications. The proposed TDCs were developed using tapped delay-line (TDL) cells in fieldprogrammable gate arrays (FPGAs). With the MB method, we implemented a resolution-adjustable TDC showing excellent linearity in Xilinx UltraScale FPGAs. We demonstrate a 128-channel TDC to show that the proposed method is cost-effective in logic resources. We also developed a software tool to predict the performances of TDL-based TDCs robustly. Results from both software analysis and hardware implementations are in good agreement and show that the proposed design has great potential for multichannel applications; the averaged − and − are close to or even less than 0.05 LSB in multichannel designs. Index Terms-Light detection and ranging (LiDAR), Timeto-digital converters (TDCs), Time-of-flight (ToF), Fieldprogrammable gate arrays (FPGAs)

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Section: Introductionmentioning

confidence: 99%

“…However, for TDCs with an extended measurement range (> 500 ns), onboard histogramming modules cost significant BRAM resources, not suitable for multichannel TDC designs. Therefore, many previously reported TDCs with long measurement ranges can only post-process data in PCs [35], [37], [41], [42].…”

Section: Introductionmentioning

confidence: 99%

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

Xie

Wang

Chen

et al. 2022

IEEE Trans. Ind. Electron.

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“…To avoid circuit metastability associated with narrow pulse widths, both fractional period widths are extended by one 𝑇 𝐶𝐿𝐾 with circuit shown in Fig. 1(b) [12] to result in timing diagram shown in Fig. 1(c).…”

Section: Introductionmentioning

confidence: 99%

“…The rest of this section will mainly discuss about the prior arts on fine TDC developments. There are multiple prior techniques employed in the implementation of fine FPGA TDCs, such as large-scale phase matrix (LSPM) [12][13], wave union [14][15], Vernier delay lines [16][17] and tapped delay line (TDL). Several approaches of TDL technique have been demonstrated in prior arts, such as TDL utilizing uniform taps [18] and non-uniform taps [19].…”

Section: Introductionmentioning

confidence: 99%

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

et al. 2022

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A field-programmable gate array (FPGA) high-resolution time-to-digital converter (TDC) based on phase-wrapping, sorting, and selection to achieve an extremely fine bin size of 1 ps is proposed in this paper. Based on Nutt interpolation method, a wide measurement range with a high resolution can be realized at the same time. The input signal is fed into tapped delay lines (TDL) with regularized and automated cell placements to generate a multitude of delayed signals with plenty of regularized phase shifts. Due to periodicity, those phase shifts will be equivalently wrapped within a reference clock period and then phase sorting, ROM-based selection are applied to construct a merged TDL with uniform phase division across the reference clock period. The FPGA TDC was implemented successfully on both Altera Stratix IV to achieve a resolution as fine as 1ps with a measurement range of 1s. The short-range integral non-linearity errors (INL) are measured as -1.470 -1.676 LSB for Stratix IV to demonstrate its excellent linearity.INDEX TERMS Field programmable gate array (FPGA), merged TDL, phase selection, phase sorting, phase wrapping, time-to-digital converter.

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“…For the application of TOF-PET [7][8][9]15,16], it can determine the position accurately by measuring the time difference between the tracer within the response line, and the multi-channel TDCs are required for measuring the time difference accurately to reconstruct the images. Numerous researchers have implemented TDCs in field-programmable gate arrays (FPGAs) due to their low cost, low development time, and flexibility [17][18][19][20][21][22][23][24][25][26][27][28][29][30][31]. The time resolution and linearity are important parameters in FPGA-based TDC designs [17]; however, the process variation in the fabrication of FPGAs can lead to serious nonlinearity.…”

Section: Introductionmentioning

confidence: 99%

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

Chen

2020

Electronics

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This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

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High-Precision PLL Delay Matrix With Overclocking and Double Data Rate for Accurate FPGA Time-to-Digital Converters

Cited by 17 publications

References 32 publications

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

128-Channel High-Linearity Resolution-Adjustable Time-to-Digital Converters for LiDAR Applications: Software Predictions and Hardware Implementations

A 1-ps Bin Size 4.87-ps Resolution FPGA Time-to-Digital Converter Based on Phase Wrapping Sorting and Selection

Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

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