High Pinout IC Packaging and the Density Advantage of Surface Mounting

Knausenberger, Wulf; Teneketges, N.

doi:10.1109/tchmt.1983.1136191

Cited by 9 publications

(2 citation statements)

References 1 publication

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“…However, the increase in interconnections must be consistent withthe limits on interconnection wires. 13 Aside from the short interconnections appearing among logic gates within a logic function, interconnections generally connect one planar circuit area with another planar circuit area. Whereas the complexity of a logic function increases with that area, the number of external interconnections to that area typically is proportional to the edge dimension of the circuit area.…”

Section: Physical Performance Issuesmentioning

confidence: 99%

Fundamental Interconnection Issues

Hornak¹,

Little²,

Tewksbury³

et al. 1987

At&T Technical Journal

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This paper presents several current interconnection issues as well as future technological directions for improved interconnection/communication performance. The physical hierarchy of interconnections and the corresponding communication environment are highlighted. General issues concerning chip‐to‐chip and on‐chip interconnections are reviewed, with particular emphasis on chip or wafer‐level clock distribution. Finally, wafer‐scale related system modules and optical interconnections are discussed from a “macro‐integration” perspective.

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Section: Physical Performance Issuesmentioning

confidence: 99%

Fundamental Interconnection Issues

Hornak¹,

Little²,

Tewksbury³

et al. 1987

At&T Technical Journal

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“…Thus, the footprint of the via space is available for routing on allother signal layers. 8 These factors lead naturally to designing structures that are optimized for surface mounting (and are less suitable for through-hole components). Figure 9 shows such a structure.…”

Section: Packaging Requirementsmentioning

confidence: 99%

Interconnection System Requirements and Modeling

Pinnel

Knausenberger

1987

At&T Technical Journal

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M. Robert Pinnel is head of the Systems Analysis and Technology Planning Department at AT&T Bell Laboratories in Whippany. New Jersey. and Wulf H. Knausenbergeris a supervisor in that department. Mr: Pinnel is responsible for trend analysis, long-range planning, and development of advanced applications for interconnection technology and hardware. He joined the company in 1970 and has a B.S. in electrical engineering, an M.S. in metallurgy. and a Ph.D. in materials engineering, all from Drexel University Mr: Knausenberger is responsible for interconnection system analysis and project planning. He joined the company in 1970 and has a B.S. in engineering science and a Ph.D. in solidstate science, both from Pennsylvania State UniversityRapid technological advances in electronic systems technologies are placing increasingly severe demands on interconnection media. One primary driving force is the evolutionary advance in the scale of integration in silicon with its inherent cost and performance advantages. Another is the revolutionary development of photonics, which is rapidly integrating into most levels of the interconnection hierarchy. Increasingly, the interconnection environment dominates and limits the performance of large-scale electronic systems. This paper explores traditional levels of interconnection from Ie chip packages to frames. It shows how the interconnection levels interrelate and must be improved simultaneously to achieve full performance and cost benefits. The first major step in this evolution is well underway with the rapid transition to surface mounting of devices. We describe advanced modeling tools and relate the results of modeling analysis to the challenges faced by interconnection technology hardware and materials. PerspectiveDriven byrapid evolutionary and revolutionary technological advances, the electronics industry is enteringa period ofsignificant growth and change. Formany years, the dual in-line package (DIP) served the needsforpackaging silicon chips. Conventional printed-wiring substrates, connectors, andbackplanes have successfully interconnected the various silicon and othercomponents that dothe systemfunctions.However, many believe that the DIP has run out of steam' and new integrated circuit (IC) packaging technologies are required. This has implications on each succeeding level of interconnection up to the full-system level, and a large-scale electronic system's performance 45

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Package Wiring and Terminals

Heller¹,

Mikhail²

1989

Microelectronics Packaging Handbook

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High Pinout IC Packaging and the Density Advantage of Surface Mounting

Cited by 9 publications

References 1 publication

Fundamental Interconnection Issues

Fundamental Interconnection Issues

Interconnection System Requirements and Modeling

Package Wiring and Terminals

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