High-Performance Single-Crystal-Like Nanowire Poly-Si TFTs With Spacer Patterning Technique

Abstract

In this letter, high-performance single-crystal-like nanowire poly-Si TFTs with simple spacer patterning technique were demonstrated and characterized. Due to the nanoscale dimension formed by spacer patterning technique, each nanowire is easily transformed within one crystalline grain of the standard sequential-lateral-solidification (SLS) poly-Si film with the regularly arranged grains and thus performed with a single-crystallike device channel. Due to the high-crystallinity channel, together with the tri-gated structure, the fabricated devices revealed good device integrity of high field-effect mobility of 477 cm(2)/V . s and good ON/OFF current ratio of 1.07 x 10(8)

Performance improvement of a sol–gel ZTO-based TFT due to an interfacial SnOxdopant layer

“…This phenomenon can be caused by high contact resistance between the electrode and the semiconductor layer. 70–73…”

High-Performance Poly-Si Thin-Film Transistors With L-Fin Channels

“…The highly improved performances of the LFin-Ni-NH 3 can be attributed to the employment of a double-gate structure which provides higher gate controllability. Compared to the TFTs with a NW structure [15], [16], the LFin-Ni-NH 3 devices have good SS and comparable DIBL, using a simpler process.…”

Characteristics of Gate-All-Around Junctionless Polysilicon Nanowire Transistors With Twin 20-nm Gates

“…Moreover, both nanowire channel and gate length were for the first time prepared via the same technique. Although some other reports presented different top-down fabrication approaches to obtain very small poly-Si NW channel [5], [7], [8], these techniques are either too complex or too difficult to define the gate length. Therefore, the gate lengths of reported devices were usually above 0.35 µm.…”

“…In order to fully deplete the channel by gate electrostatic field, the channel dimension needs to be scaled down close to 10 nm [1]. There are several reports of JL and inversion-mode (IM) transistors having very small nanowire (NW) channels made by interesting top-down approaches and I-line photolithography (365 nm) [5], [7], [8] without using expensive lithographic tools like ArF photolithography (193 nm) [9] or electron beam (E-beam) writer. However, most of these top-down approaches are complex and difficult to define the gate length, and the devices still possess large gate length (L G > 0.35 µm).…”

“…Therefore, poly-Si NW devices with sub-50 nm L G usually require an e-beam lithography tool [10], [11]. Among those reporting these interesting top-down approaches, the sidewall spacer is a commonly used method to create a nanoscale hard mask for nanowire channel [8] and lightly-doped drain (LDD) structure [12]. Such a patterning technique can produce a feature size down to 7 nm, as well as uniformity superior to the e-beam lithography and trimming process [13].…”