High-performance routing trees with identified critical sinks

Boese, Kenneth D.; Kahng, Andrew B.; Robins, Gabriel

doi:10.1145/157485.164662

Cited by 63 publications

(46 citation statements)

References 25 publications

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“…For example, the Elmore delay model was used in [24] and the 2-pole delay model was used in [25] to evaluate which node or edge to be added to the routing tree during iterative tree construction. Other methods, such as the alphabetical tree and P-tree construction are also summarized in [3].…”

Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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I. INTERCONNECT TRENDS AND CHALLENGESThe driving force behind the impressive advancement of the VLSI circuit technology has been the rapid scaling of the feature size, i.e., the minimum dimension of the transistor. Table I lists the main characteristics of each technology generation in the NTRS. Such rapid scaling has two profound impacts. First, it enables much higher degree of on-chip integration. The number of transistors per chip will increase by more than 2 per generation to reach 800 millions in the© ¢ m technology. Second, it implies that the circuit performance will be increasingly determined by the interconnect performance. The interconnect design will play the most critical role in achieving the projected clock frequencies in the NTRS. This paper presents the trends and challenges of interconnect design in current and future technologies and discusses the available solutions.In order to better understand the significance of interconnect design in the future technology generations, we performed a number of experiments based on the interconnect parameters provided in the NTRS as shown in the bold face in Table II global interconnects, we also derived the interconnect parameters for the M4 layer,c which are also shown in Table II. Furthermore, we derived a set of device parameters as shown in Table III based on the data on processes and device in the NTRS. Using these sets of parameters, we carried out extensive simulations using HSPICE to quantitatively measure the interconnect performance and reliability in future technology generations and obtained the following results:(1) Interconnect delay is clearly the dominating factor in determincWe assume that the minimum width and spacing of M4 is 2.5 times those of M1. The aspect ratios 7 6 8 and 7 6 A @ are used to determine the metal thickness and the dielectric thickness for all layers. For M1, we assume that the substrate and M2 are the ground planes; and for M4, we assume that M3 and M5 are the ground planes. The total capacitance, including the area capacitance, fringing capacitance, and coupling capacitance components, are obtained using the 3D field solver FastCap [2]. Based on these assumptions, our capacitance values for M1 closely match those given in the NTRS.

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Section: B Interconnect Topology Optimizationmentioning

confidence: 99%

Interconnect design for deep submicron ICs

Cong

Pan

et al. 1997

Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) ICCAD-97

124

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“…For example, interconnect topologies such as maximum performance trees [4], A-trees [8], and lowdelay trees [1] have been proposed to minimize interconnect delay. Interconnect delay can be further reduced by sizing device and wire.…”

Section: Introductionmentioning

confidence: 99%

Simultaneous buffer and wire sizing for performance and power optimization

Cong¹,

Koh²,

Leung³

Proceedings of 1996 International Symposium on Low Power Electronics and Design

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In this paper, we study the simultaneous buffer and wire sizing (SBWS) problem for delay and power dissipation minimization. We prove the BS/WS relation for optimal SBWS solutions. This relation leads to a polynomial time algorithm for computing the lower and upper bounds of the optimal SBWS solutions, which enables an efficient optimal algorithm for computing optimal SBWS solutions. We have applied the SBWS algorithms to the clock nets in a spread spectrum IF transceiver chip and HSPICE simulations show that our algorithms can reduce skew and power by a factor of 3:5X and 2:6X, respectively, when compared to the manual layout of the clock nets in the original chip.

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“…Discrepancies between the characteristics of the two could lead to incorrect assumptions, causing the placer to create inappropriate placement for the final route. In this preliminary implementation, routing on the region-based graph was performed by an A* algorithm [2]. The algorithm initially sorts the sinks in order of criticality (manhattan distance to source).…”

Section: The Region Routermentioning

confidence: 99%

“…The dynamic behavior of this graph supports increasingly accurate supply-demand modeling at each iteration of the algorithm. The current implementation of the supply-demand algorithm creates global routes between regions using an A* search [2] algorithm and computes internal costs using a line-probe [3] heuristic. However, this component of the algorithm can be replaced with any appropriate route model.…”

Section: Introductionmentioning

confidence: 99%

Congestion driven quadratic placement

Parakh¹,

Brown²,

Sakallah³

Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)

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This paper introduces and demonstrates an extension to quadratic placement that accounts for wiring congestion. The algorithm uses an A* router and line-probe heuristics on region-based routing graphs to compute routing cost. The interplay between routing analysis and quadratic placement using a growth matrix permits global treatment of congestion. Further reduction in congestion is obtained by the relaxation of pin constraints. Experiments show improvements in wireability.

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High-performance routing trees with identified critical sinks

Cited by 63 publications

References 25 publications

Interconnect design for deep submicron ICs

Interconnect design for deep submicron ICs

Simultaneous buffer and wire sizing for performance and power optimization

Congestion driven quadratic placement

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